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PART:
2X
150MHz
X
166MHz
180MHz
200MHz
NOTE:
1. Only those indicated here are tested during the manufacturing test process.
Table 11-11. GTL+ Signal Groups A.C. Specifications
T#
Parameter
T7A: GTL+ Output Valid Delay
→
H
L
T7B: GTL+ Output Valid Delay
→
L
H
T8:
GTL+ Input Setup Time
T9:
GTL+ Input Hold Time
T10: RESET# Pulse Width
NOTES:
1. Valid delay timings for these signals are specified into an idealized 25Ω resistor to 1.5V with V REF at
1.0V. Minimum values guaranteed by design. See Figure 12-11 for the actual test configuration.
2. GTL+ timing specifications for 166MHz and higher components are PRELIMINARY. Consult your
local FAE.
3. A minimum of 3 clocks must be guaranteed between 2 active-to-inactive transitions of TRDY#.
4. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
5. Specification takes into account a 0.3V/ns edge rate and the allowable V REF variation.
Guaranteed by design.
6. After V cc , V TT , V REF , BCLK and the clock ratio become stable.
Table 11-10. Supported Clock Ratios
5/2X
3X
X
X
X
X
R L = 25Ω terminated to 1.5V, V REF = 1.0V
Min
Max
0.55
4.4
0.80
4.4
0.55
3.9
0.80
3.9
2.2
0.45
0.70
1
ELECTRICAL SPECIFICATIONS
1
7/2X
X
X
X
X
Unit
Figure
ns
11-8
@ 150MHz, 256K L2
ns
All other components
1 , 2
ns
11-8
@ 150MHz, 256K L2
ns
All other components
1
3 , 4 , 5
ns
11-9
ns
11-9
@ 150MHz, 256K L2
ns
All other components
5
6
ms
11-12
11-13
4X
X
Notes
11-19
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