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4.5.2.3.
IMPLICIT WRITEBACK ON A READ TRANSACTION
Figure 4-16 shows a read transaction with an implicit writeback. TRDY# is asserted in this op-
eration because there is writeback data to transfer. Note that the implicit writeback response
must be asserted exactly one clock after valid TRDY# assertion is sampled. That is, TRDY# is
sampled active and DBSY# is sampled inactive.
CLK
ADS#
REQ0#
HITM#
TRDY#
RS[2:0]#
DBSY#
{scnt}
{rcnt}
Figure 4-16. RS[2:0]# Activation with Snoop Initiated TRDY#
A transaction is issued in T1. The REQa0# pin indicates a read transaction, so TRDY# is as-
sumed not needed for this transaction.
But snoop results observed in T6 indicate that an implicit writeback will occur (HITM# is as-
serted), therefore a TRDY# assertion is needed. Since the response for the previous transaction
is complete, and no request initiated TRDY# assertion is needed, TRDY# for the implicit write-
back is asserted in T7. (TRDY# assertion due to an implicit writeback is called a snoop initiated
TRDY#.) Since DBSY# is observed inactive in T7, TRDY# can be deasserted in one clock in
T8, but need not be deasserted until the response is driven on RS[2:0]#.
In T9, one clock after the observation of active TRDY# with inactive DBSY# for the implicit
writeback, the Implicit Writeback Response must be driven on RS[2:0]# and the data is driven
on the data bus. This makes the data transfer and response behave like both a read (for the re-
questing agent) and a write (for the addressed agent).
1
2
3
4
5
6
0
0
1
1
1
1
0
0
1
1
1
1
BUS PROTOCOL
7
8
9
10
11
12
0
0
0
0
0
0
1
1
1
1
0
0
4-29
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