Pd Port Group - Epson S1C31W65 Technical Manual

7 I/O PORTS (PPORT)

7.7.8 Pd Port Group

The Pd port group supports the GPIO function. Two ports Pd0–Pd1 are configured as debugging function ports at
initialization.
Register name Bit
PPORTPDDAT 15–8 PDOUT[7:0]
(Pd Port Data
7–5 PDIN[7:5]
Register)
4
3–0 PDIN[3:0]
PPORTPDIOEN 15–13 PDIEN[7:5]
(Pd Port Enable
12
Register)
11–8 PDIEN[3:0]
7–0 PDOEN[7:0]
PPORTPDRCTL 15–13 PDPDPU[7:5]
(Pd Port Pull-up/down
12
Control Register)
11–8 PDPDPU[3:0]
7–5 PDREN[7:5]
4
3–0 PDREN[3:0]
PPORTPDINTF 15–0 –
PPORTPDINTCTL
PPORTPDCHATEN
PPORTPDMODSEL 15–8 –
(Pd Port Mode Select
7–0 PDSEL[7:0]
Register)
PPORTPDFNCSEL 15–14 PD7MUX[1:0]
(Pd Port Function
13–12 PD6MUX[1:0]
Select Register)
11–10 PD5MUX[1:0]
9–8 (reserved)
7–6 PD3MUX[1:0]
5–4 PD2MUX[1:0]
3–2 PD1MUX[1:0]
1–0 PD0MUX[1:0]
PdSELy = 0
Port
name
GPIO
Peripheral
Pd0 Pd0 CPU
Pd1 Pd1 CPU
Pd2 Pd2
Pd3 Pd3
Pd4 Pd4
Pd5 Pd5
Pd6 Pd6
Pd7 Pd7
7-18
Table 7.7.8.1 Control Registers for Pd Port Group
Bit name Initial
0x00
0x0
(reserved)
0x00
0x0
(reserved)
0x0
0x10
0x0
(reserved)
0x0
0x0
(reserved)
0x0
0x0000
0x00
0x23
0x0
0x0
0x2
0x0
0x0
0x0
0x0
0x0
Table 7.7.8.2 Pd Port Group Function Assignment
PdyMUX = 0x0 PdyMUX = 0x1
(Function 0) (Function 1)
Pin Peripheral
SWCLK –
SWD –
– – –
– – –
– – –
– – –
– – –
– – –
Seiko Epson Corporation
Reset R/W
H0 R/W –
H0 R
0 – R
H0 R
H0 R/W –
0 H0 R/W
H0 R/W
H0 R/W
H0 R/W –
0 H0 R/W
H0 R/W
H0 R/W
0 H0 R/W
H0 R/W
– R –
– R –
H0 R/W
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
PdSELy = 1
PdyMUX = 0x2
(Function 2)
Pin Peripheral
– –
– –
– CLG
– CLG
– –
– FLASHC
– LCD8D
– LCD8D
Remarks
PdyMUX = 0x3
(Function 3)
Pin Peripheral Pin
– – –
– – –
OSC3 – –
OSC4 – –
– – –
V – –
PP
C – –
P1
C – –
P2
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)