Pd Port Group - Epson S1C31W74 Technical Manual

7.7.11 Pd Port Group

The Pd port group consists of four ports Pd0–Pd3 and two ports Pd0–Pd1 are configured as debugging function
ports at initialization. These four ports support the GPIO function.
Register name Bit
PPORTPDDAT 15–12 –
(Pd Port Data
11–8 PDOUT[3:0]
Register)
7–4 –
3–0 PDIN[3:0]
PPORTPDIOEN 15–12 –
(Pd Port Enable
11–8 PDIEN[3:0]
Register)
7–4 –
3–0 PDOEN[3:0]
PPORTPDRCTL 15–12 –
(Pd Port Pull-up/down
11–8 PDPDPU[3:0]
Control Register)
7–4 –
3–0 PDREN[3:0]
PPORTPDINTF 15–0 –
PPORTPDINTCTL
PPORTPDCHATEN
PPORTPDMODSEL 15–8 –
(Pd Port Mode Select
7–4 –
Register)
3–0 PDSEL[3:0]
PPORTPDFNCSEL 15–8 –
(Pd Port Function
7–6 PD3MUX[1:0]
Select Register)
5–4 PD2MUX[1:0]
3–2 PD1MUX[1:0]
1–0 PD0MUX[1:0]
PdSELy = 0
Port
name
GPIO
Peripheral
Pd0 Pd0 CPU
Pd1 Pd1 CPU
Pd2 Pd2
Pd3 Pd3
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
Table 7.7.11.1 Control Registers for Pd Port Group
Bit name Initial
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0000
0x00
0x0
0x3
0x00
0x0
0x0
0x0
0x0
Table 7.7.11.2 Pd Port Group Function Assignment
PdyMUX = 0x0 PdyMUX = 0x1
(Function 0) (Function 1)
Pin Peripheral
SWCLK –
SWD –
– – –
– – –
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
– R
x H0 R
– R –
H0 R/W
– R
H0 R/W
– R –
H0 R/W
– R
H0 R/W
– R –
– R –
– R
H0 R/W
– R –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
PdSELy = 1
PdyMUX = 0x2
(Function 2)
Pin Peripheral
– –
– –
– CLG
– CLG
7 I/O PORTS (PPORT)
Remarks
PdyMUX = 0x3
(Function 3)
Pin Peripheral Pin
– – –
– – –
OSC3 – –
OSC4 – –
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