Flashc Flash Read Cycle Register - Epson S1C17W14 Technical Manual

Bits 2–0 IRAMSZ[2:0]
These bits set the internal RAM size that can be used.

FLASHC Flash Read Cycle Register

Register name Bit
FLASHCWAIT 15–8 –
7
6–2 –
1–0 RDWAIT[1:0]
Bits 15–8 Reserved
Bit 7 XBUSY
This bit indicates whether the Flash memory can be accessed or not.
1 (R): Flash memory ready to access
0 (R): Flash access prohibited
The Flash memory can always be accessed during normal operation.
Bits 6–2 Reserved
Bits 1–0 RDWAIT[1:0]
These bits set the number of bus access cycles for reading from the Flash memory.
Table 4.7.2 Setting Number of Bus Access Cycles for Flash Read
When V = 1.2 to 1.6 V
DD
FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles
When V = 1.6 to 3.6 V
DD
FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles
Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.
S1C17W14/W16 TECHNICAL MANUAL
(Rev. 1.2)
Table 4.7.1 Internal RAM Size Selections
MSCIRAMSZ.
IRAMSZ[2:0] bits
0x7–0x5
0x4
0x3
0x2
0x1
0x0
Bit name Initial
0x00
XBUSY
0x00
0x1
0x3
0x2
0x1
0x0
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Internal RAM size
S1C17W14 S1C17W16
Reserved Reserved
Reserved
4KB
2KB
1KB
512B 512B
Reset R/W
– R –
0 H0 R
– R
H0 R/WP
System clock frequency
4
3
2
1
System clock frequency
4
3
2
1
4 MEMORY AND BUS
8KB
4KB
2KB
1KB
Remarks
1.1 MHz (max.)
1.1 MHz (max.)
1.1 MHz (max.)
800 kHz (max.)
4.2 MHz (max.)
4.2 MHz (max.)
4.2 MHz (max.)
2.1 MHz (max.)
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