Functional Description; Pci Bus Protocol; Pci Bus Background - Freescale Semiconductor MCF5480 Reference Manual

Bits Name
31–7 —
6–0 WritePtr
19.4

Functional Description

The MCF548x PCI module provides both master and target PCI bus interfaces as shown in
The internal master, or initiator, interface is accessible by any XL bus master, such as the processor core,
and also provides a DMA interface through the communication subsystem that can be accessed by the
multichannel DMA engine. The target interface provides external PCI masters access into two memory
windows of MCF548x address space. PCI arbitration is handled external to this module, by either the
MCF548x internal PCI arbiter or arbitration off-chip
The registers, described in
information about multiple interfaces. An additional configuration interface allows internal access through
the slave bus to the PCI Type 0 Configuration registers, which are accessible to both the MCF548x and to
external masters through the PCI bus.
The following sections describe the operation of the PCI module.
19.4.1

PCI Bus Protocol

This section will provide a simple overview of the PCI bus protocol, including some details of MCF548x
implementation. For details regarding PCI bus operation, refer to the PCI Local Bus Specification,
Revision 2.2.

19.4.1.1 PCI Bus Background

The PCI interface is synchronous and is best used for bursting data in large chunks. Its maximum
bandwidth approaches 266 Megabytes per second for the 32-bit implementation running at 66 MHz. A
system will contain one device that is responsible for configuring all other devices on the bus upon reset.
Each device has 256 bytes of configuration space that define individual requirements to the system
controller. These registers are read and written through a "configuration access" command. A PCI transfer
is started by the master and is directed toward a specific target. A provision is made for broadcasting to
several targets through the "special command". Data is transferred through the use of memory and I/O read
and write commands.
19-48
Table 19-45. PCIRFWPR Field Descriptions
Reserverd, should be cleared.
This value is maintained by the FIFO hardware and is not normally written by the user. It can be
adjusted in special cases but will of course disrupt the integrity of the data flow. This value
represents the Write address being presented to the FIFO RAM.
Section 19.3, "Memory Map/Register Definition,"
Table 19-46. PCI Command Encodings
PCICXBE[3:0]
0000
0001
0010
0011
0100
MCF548x Reference Manual, Rev. 3
Description
(Chapter 20, "PCI Bus Arbiter
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Figure 19-1.
Module").
control and provide
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