Sci Data Register (Scix_D) - Freescale Semiconductor MC9S08PT60 Reference Manual

Register definition
Field
1 Framing Error Interrupt Enable
FEIE
This bit enables the framing error flag (FE) to generate hardware interrupt requests.
0 FE interrupts disabled; use polling).
1 Hardware interrupt requested when FE is set.
0 Parity Error Interrupt Enable
PEIE
This bit enables the parity error flag (PF) to generate hardware interrupt requests.
0 PF interrupts disabled; use polling).
1 Hardware interrupt requested when PF is set.

15.3.8 SCI Data Register (SCIx_D)

This register is actually two separate registers. Reads return the contents of the read-only
receive data buffer and writes go to the write-only transmit data buffer. Reads and writes
of this register are also involved in the automatic flag clearing mechanisms for the SCI
status flags.
Address: Base address + 7h offset
Bit 7
Read
R7T7
Write
Reset
0
Field
7 Read receive data buffer 7 or write transmit data buffer 7.
R7T7
6 Read receive data buffer 6 or write transmit data buffer 6.
R6T6
5 Read receive data buffer 5 or write transmit data buffer 5.
R5T5
4 Read receive data buffer 4 or write transmit data buffer 4.
R4T4
3 Read receive data buffer 3 or write transmit data buffer 3.
R3T3
2 Read receive data buffer 2 or write transmit data buffer 2.
R2T2
1 Read receive data buffer 1 or write transmit data buffer 1.
R1T1
0 Read receive data buffer 0 or write transmit data buffer 0.
R0T0
428
SCIx_C3 field descriptions (continued)
6 5
R6T6 R5T5 R4T4
0 0
SCIx_D field descriptions
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Description
4 3 2
R3T3 R2T2
0 0 0
Description
1 0
R1T1 R0T0
0 0
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