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PXN20 Microcontroller

Reference Manual

Devices Supported:

PXN2020

PXN2120

PXN20RM

Rev. 1

06/2011

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Summary of Contents for NXP Semiconductors PXN2020

Page 1 PXN20 Microcontroller Reference Manual Devices Supported: PXN2020 PXN2120 PXN20RM Rev. 1 06/2011...
Page 2 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Information in this document is provided solely to enable system and Technical Information Center software implementers to use Freescale Semiconductor products.
Page 3: Table Of Contents
Table of Contents Chapter 1 Introduction Overview ....................1-1 PXN20 Features .
Page 4 Detailed Signal Description ................3-21 3.4.1 Port A Pins .
Page 5: Pxn20 Microcontroller Reference Manual,
3.4.5.11 PE10 — GPIO (PE[10]) / eSCI_H Transmit (TXD_H) / DSPI_B Peripheral Chip Select (PCS_B[3]) ... . 3-28 3.4.5.12 PE11 — GPIO (PE[11]) / eSCI_H Receive (RXD_H) / DSPI_B Peripheral Chip Select (PCS_B[2]) ... . . 3-28 3.4.5.13 PE12 —...
Page 6 3.4.8.1 PH0 — GPIO (PH[0]) / eMIOS Channel (eMIOS[31]) / Ethernet Collision (FEC_COL) ..... . . 3-33 3.4.8.2 PH1 — GPIO (PH[1]) / eMIOS Channel (eMIOS[30]) / Ethernet Receive Data Valid (FEC_RX_DV) ... . . 3-33 3.4.8.3 PH2 —...
Page 7 MDO[0] 3- ..................39 3.4.11.5 Nexus Message Data Out MDO[11:1] 3-.
Page 8: Introduction
Chapter 4 Resets Introduction ................... . 4-1 External Signal Description .
Page 9 Chapter 6 Clocks, Reset, and Power (CRP) Introduction ................... . 6-1 6.1.1 Block Diagram .
Page 10 Resets ....................7-18 7.5.1 Clock Mode Selection .
Page 11 8.3.2.40 Masked Parallel GPIO Pin Data Output Register 4 (SIU_MPGPDO4) ........8-54 8.3.2.41 Masked Parallel GPIO Pin Data Output Register 5 (SIU_MPGPDO5) .
Page 12 10.1.3.2 Hardware Vector Mode ............... 10-6 10.2 External Signal Description .
Page 13 11.5 SRAM ECC Mechanism ................. . 11-3 11.5.1 Access Timing .
Page 14 13.1.3.2 Integer Unit Features ............... . . 13-4 13.1.3.3 Load/Store Unit Features .
Page 15 Chapter 15 Semaphores 15.1 Introduction ................... 15-1 15.1.1 Block Diagram .
Page 16 Chapter 18 Memory Protection Unit (MPU) 18.1 Introduction ................... 18-1 18.1.1 Block Diagram .
Page 17 20.3.2.7 SWT Service Key Register (SWT_SK) ............20-7 20.4 Functional Description .
Page 18 23.4.3 Always Enabled DMA Sources ..............23-11 23.5 Initialization/Application Information .
Page 19 Chapter 25 Fast Ethernet Controller (FEC) 25.1 Introduction ................... 25-1 25.1.1 Block Diagram .
Page 20 25.5.1.1 Driver/DMA Operation with Transmit BDs ............25-44 25.5.1.2 Driver/DMA Operation with Receive BDs .
Page 21 26.5.2.31 Sync Frame Counter Register (SFCNTR) ............26-42 26.5.2.32 Sync Frame Table Offset Register (SFTOR) .
Page 22 26.6.5.1 Message Buffer Protection and Data Consistency ..........26-88 26.6.5.2 Message Buffer Header Field Description .
Page 23 26.6.21Lower Bit Rate Support ................26-151 26.7 Application Information .
Page 24 Chapter 28 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.1 Introduction ................... 28-1 28.1.1 Block Diagram .
Page 25 29.3.2 Message Buffer Structure ................29-7 29.3.3 Rx FIFO Structure .
Page 26 30.3.2.6 DSPI PUSH TX FIFO Register (DSPI_PUSHR) ........... 30-19 30.3.2.7 DSPI POP RX FIFO Register (DSPI_POPR) .
Page 27 30.4.13.1 Halt Mode ................30-58 30.4.13.2 Module Disable Mode .
Page 28 31.4.6.5 LIN Error Reporting ............... . . 31-48 31.4.6.6 LIN Wakeup .
Page 29 33.4.1 Module Memory Map ................33-2 33.4.1.1 Control Status Register (CTU_CSR) .
Page 30 34.4.1.2 Start of Normal Conversion ..............34-41 34.4.1.3 Normal Conversion Operating Modes .
Page 31 Chapter 36 Nexus Development Interface (NDI) 36.1 Introduction ................... 36-1 36.2 Block Diagram .
Page 32 36.7 e200z0 Class 2+ Nexus Module (Nexus2+) ..............36-70 36.7.1 Nexus2+ Introduction .
Page 33 About This Book This reference manual describes the PXN20 microcontroller family for software and hardware developers. Information regarding bus timing, signal behavior, and AC, DC, and thermal characteristics are detailed in the device data sheet (PXN20 Microcontroller Data Sheet). The information in this book is subject to change without notice, as described in the disclaimers on the title page.
Page 34 • Chapter 6, Clocks, Reset, and Power (CRP), describes the CRP block, which manages entry into, operation during, and exit from power-saving modes; and maintains all of the control logic that requires power when other portions of the PXN20 are powered down in power-saving modes. •...
Page 35 • Chapter 24, Enhanced Direct Memory Access Controller (eDMA), describes the enhanced DMA controller implemented on the PXN20. • Chapter 25, Fast Ethernet Controller (FEC), describes the feature set, operation, and programming model of the FEC block. • Chapter 26, FlexRay Communication Controller (FlexRAY), describes the FlexRay communication controller on the PXN20 that implements the FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
Page 36 General Information Useful information about the Power Architecture and computer architecture in general: • Programming Environments Manual for 32-Bit Implementations of the PowerPC™ Architecture (MPCFPE32B) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield •...
Page 37 reserved When a bit or address is reserved, it should not be written. If read, its value is not guaranteed. Reading or writing to reserved bits or addresses may cause unexpected results. MNEMONICS In text, instruction mnemonics are shown in uppercase. In code and tables, instruction mnemonics are shown in lowercase.
Page 38 The following descriptions are used in register bit field description tables: Indicates a reserved bit field in a memory-mapped register. These bits are always read as 0. Indicates a reserved bit field in a memory-mapped register. These bits are always read as 1. R FIELDNAME Indicates a read/write bit in a memory-mapped register.
Page 39 Table i. Acronyms and Abbreviated Terms (continued) Term Meaning JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out Least-significant byte Low-voltage interrupt Least-significant bit Multiply accumulate unit, also Media access controller Most-significant byte Most-significant bit Multiplex No operation Operand execution pipeline...
Page 40 Table ii. Notational Conventions (continued) Instruction Operand Syntax Register Specifications Any address register n (example: A3 is address register 3) Ay,Ax Source and destination address registers, respectively Any data register n (example: D5 is data register 5) Dy,Dx Source and destination data registers, respectively Any control register (example VBR is the vector base register) MAC registers (ACC, MAC, MASK) Any address or data register...
Page 41 Table ii. Notational Conventions (continued) Instruction Operand Syntax Arithmetic division Invert; operand is logically complemented & Logical AND Logical OR Logical exclusive OR << Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits) ...
Page 42 PXN20 Microcontroller Reference Manual, Rev. 1 lxiv Freescale Semiconductor...
Page 43: Overview
Chapter 1 Introduction Overview ® The PXN20 products are compatible 32-bit microcontrollers built on Power Architecture technology. This document describes the available features, and highlights important characteristics of the devices. The PXN20 products are designed to address the need for single chip industrial networking applications and are tailored to address the need for high performance and high memory size while keeping the power consumption low.
Page 44 Introduction Table 1-1. PXN20 Family Feature Set Feature PXN20 PXN21 Memory Protection Unit (MPU) 16 entry Direct Memory Access Unit (eDMA) 16 Channel 32 Channel Ethernet (FEC) MediaLB (MLB-DIM) FlexRay Controller Yes (128 Message Buffers) Analog-to-Digital Converter (ADC) 36 internal channels, 10-bit 64 internal channels, 10-bit Supports 32 external Supports 32 external...
Page 45: Pxn20 Block Diagram
Introduction Similarly, the e200z0 core is also referred to as the Z0. PXN20 Block Diagram Figure 1-1 shows a top-level block diagram of the PXN20. PXN20 Block Diagram Debug 32 kHz 4-40 MHz 16 MHz VREG XTAL XTAL Controller JTAG Masters e200z650 Core Nexus3 (Z6)
Page 46: Pxn21 Block Diagram
Introduction PXN21 Block Diagram Figure 1-2 shows a top-level block diagram for the PXN21. PXN21 Block Diagram Debug 32 kHz 4–40 MHz 16 MHz VREG XTAL XTAL Controller JTAG Masters e200z650 Core Nexus3 (Z6) RTC/API 128 kHz FMPLL Nexus2+ (Z0) MMU (32 TLB) Semaphores FPU/SPE...
Page 47: Critical Performance Parameters
Introduction Critical Performance Parameters The critical performance parameters of the PXN20 devices feature the following: Fully static design operation up to a maximum of 116 MHz, based on 105 C ambient • • Temperature range –40° to 105 °C ambient temperature •...
Page 48: Packages
Introduction – In SLEEP mode, the 16 MHz IRC can be enabled to continue to run and may be selected to clock the RTC and API – In SLEEP mode, the 128 kHz IRC can be enabled to run and may be selected to clock the RTC and API –...
Page 49: I/O Processor High Performance E200Z0 Core (Iop)
Introduction • Signal processing engine (SPE) auxiliary processing unit (APU) operating on 64-bit general purpose registers • Floating point ® — IEEE 754 compatible with software wrapper — Single precision in hardware; double precision with software library — Conversion instructions between single precision floating point and fixed point •...
Page 50 Introduction — Each port supported with separate page buffers • Flash page buffers to improve access time to code and data held in flash — 4  128-bit page buffers with programmable prefetch control for flash access — Page buffers can be allocated for code-only, fixed partitions of code and data, all available for any access •...
Page 51: On-Chip Sram
Introduction 1.7.4 On-Chip SRAM On-chip SRAM on the PXN20 family features the following: • Up to 592/128 KB general purpose RAM • Two RAM blocks implemented on separate crossbar ports to reduce arbitration events for high access master to on-chip RAM. —...
Page 52: Analog To Digital Converter Module (Adc)
Introduction • Retransmission from transmit FIFO following a collision (no system bus utilization) • Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no system bus utilization) • Address recognition • RMON and IEEE statistics •...
Page 53: Cross Triggering Unit (Ctu)
Introduction • Supports operation of ADC using internal 16 MHz RC oscillator • All unused analog pins available as general purpose input pins • Selected unused analog pins available as general purpose output pins • Power-down mode • Supports for DMA transfer of results 1.7.8 Cross Triggering Unit (CTU) The CTU features the following:...
Page 54: Controller Area Network Module (Can)
Introduction — Separate transmitter and receiver CPU interrupt sources — 16-bit programmable baud-rate modulus counter and 16-bit fractional — 2 receiver wake-up methods • LIN features: — Autonomous LIN frame handling — Message buffer to store identifier and up to eight data bytes —...
Page 55: Inter-Ic Communications Module (I2C)
Introduction • Programmable clock source — System clock — Direct oscillator clock to avoid PLL jitter — Listen only mode capabilities 1.7.11 Inter-IC Communications Module (I The I C module features the following: • Two-wire bi-directional serial bus for on-board communications •...
Page 56: Enhanced Modular Input Output System (Timers - Emios200)
Introduction • Serialization of selected sources (eMIOS channels and Phantom ports in SIU) 1.7.13 Enhanced Modular Input Output System (Timers - eMIOS200) The PXN20 family implement a scaled-down version of the eMIOS module: • Supports timed I/O channels with 16-bit counter resolution •...
Page 57: Enhanced Direct Memory Access Controller (Edma)
Introduction 1.7.16 Enhanced Direct Memory Access Controller (eDMA) The following summarizes the PXN20 implementation of the eDMA controller: • Support independent 8, 16 or 32 bit single value or block transfers • Supports variable sized queues and circular queues • Source and destination address registers are independently configured to post-increment or remain constant •...
Page 58: Interrupt Controller (Intc)
Introduction 1.7.19 Interrupt Controller (INTC) The PXN20 implements an interrupt controller that features the following: • Unique 9-bit vector for each of the 316 separate interrupt sources (22 reserved) • 8 software triggerable interrupt sources • 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source •...
Page 59: System Integration Unit (Siu)
Introduction — Trimming registers to support frequency adjustment with in-application calibration • Dedicated internal 128 kHz internal RC oscillator for low power mode operation and self wake-up — 5% accuracy (after factory trim) — Trimming registers to support improve accuracy with in-application calibration •...
Page 60: Dual-Channel Flexray Controller (Fr)
Introduction 1.7.24 Dual-Channel FlexRay Controller (FR) The dual-channel FlexRay controller features the following: • Full implementation of FlexRay Protocol Specification 2.1, RevA • Single channel support — FlexRay Port A can be configured to be connected either to physical FlexRay channel A or physical FlexRay channel B •...
Page 61: Media Local Bus (Mlb)
Introduction 1.7.25 Media Local Bus (MLB) The following summarizes the MLB configuration: • Support of 16 logical channels running at a maximum speed of 1024 Fs • Transmission of commands and data and reception of receive status when functioning as the transmitting device associated with a logical channel address •...
Page 62: Nexus Development Interface (Ndi)
Introduction 1.7.28 Nexus Development Interface (NDI) The NDI module is compliant with the IEEE-ISTO 5001-2003 standard. The following features are implemented, but only available on the 256 MAPBGA emulation package: • 17-bit full duplex pin interface for medium and high visibility throughput —...
Page 63: Developer Support
Introduction • Nexus supports debug through reset and low power Developer Support This family of MCUs is supported by Freescale's Tower Development System as well as a broad set of advanced debug and runtime software: • CodeWarrior • FreeMaster • •...
Page 64 Introduction PXN20 Microcontroller Reference Manual, Rev. 1 1-22 Freescale Semiconductor...
Page 65: Memory Map
Introduction Chapter 2 Memory Map Introduction This section describes the PXN20 memory map. All addresses in the device, including those that are reserved, are identified in Table 2-1. The addresses represent the physical addresses assigned to each IP block. Table 2-1. PXN20 System Memory Map Address Unimple- Unimple-...
Page 66 Introduction Table 2-1. PXN20 System Memory Map (continued) Address Unimple- Unimple- Size Region Name Comments mented on mented on (KB) Start PXS20 PXS21 0x2000_0000 0x3FFF_FFFF 524,288 Reserved for External Bus Interface SRAM (AXBS Ports S2 and S3) 0x4000_0000 0x4007_FFFF SRAM (AXBS Port S2) This 1 MB address >...
Page 67 Introduction Table 2-1. PXN20 System Memory Map (continued) Address Unimple- Unimple- Size Region Name Comments mented on mented on (KB) Start PXS20 PXS21 0xC3FC_C000 0xC3FC_FFFF Reserved 0xC3FD_0000 0xC3FD_3FFF Reserved 0xC3FD_4000 0xC3FD_7FFF Reserved 0xC3FD_8000 0xC3FD_BFFF Reserved 0xC3FD_C000 0xC3FD_FFFF FlexRay 0xC3FE_0000 0xC3FE_3FFF Reserved 0xC3FE_4000 0xC3FE_7FFF...
Page 68 Introduction Table 2-1. PXN20 System Memory Map (continued) Address Unimple- Unimple- Size Region Name Comments mented on mented on (KB) Start PXS20 PXS21 0xFFF9_8000 0xFFF9_BFFF Reserved 0xFFF9C000 0xFFF9_FFFF Reserved 0xFFFA_0000 0xFFFA_3FFF eSCI_A 0xFFFA_4000 0xFFFA_7FFF eSCI_B 0xFFFA_8000 0xFFFA_BFFF eSCI_C 0xFFFA_C000 0xFFFA_FFFF eSCI_D 0xFFFB_0000 0xFFFB_3FFF...
Page 69: Signal Description
Chapter 3 Signal Description Introduction This chapter describes signals that connect off-chip. It includes a signal properties summary, power and ground segmentation summary, package pinouts, and detailed descriptions of signals. Because the PXN20 comes in multiple packages, some signals may not be available on every package. Refer to the PXN20 Microcontroller Data Sheet for electrical characteristics.
Page 70 Signal Description Table 3-1. PXN20 Signal Properties Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset Port A (16) PA[0] Port A GPI — — AN[0] ADC Analog Input — — — —...
Page 71 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PA10 PA[10] Port A GPI — — AN[10] ADC Analog Input — — — — PA11 PA[11] Port A GPI...
Page 72 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PB[4] Port B GPIO — — DDE1 AN[20] ADC Analog Input — — — — PB[5] Port B GPIO —...
Page 73 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PB15 PB[15] Port B GPIO — — DDE1 AN[31] ADC Analog Input PCS_D[4] DSPI_D Peripheral Chip Select —...
Page 74 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PC[9] Port C GPIO — — DDE1 AN[41] ADC Analog Input FR_DBG1 FlexRay Debug — —...
Page 75 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PD[3] Port D GPIO — — DDE2 CNRX_B FlexCAN_B Receive — — — — PD[4] Port D GPIO —...
Page 76 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PD14 PD[14] Port D GPIO — — DDE2 TXD_B eSCI_B Transmit — — — — PD15 PD[15] Port D GPIO...
Page 77 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PE[8] Port E GPIO — — DDE2 TXD_G eSCI_G Transmit PCS_A[1] DSPI_A Peripheral Chip Select —...
Page 78 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PF[2] Port F GPIO — — DDE2 SIN_A DSPI_A Serial Data In — — — —...
Page 79 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PF13 PF[13] Port F GPIO — — DDE3 SOUT_D DSPI_D Serial Data Out — — —...
Page 80 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PG[7] Port G GPIO — — DDE3 PCS_C[2] DSPI_C Peripheral Chip Select FEC_MDIO Ethernet Mgmt. Data I/O AN[55] ADC Analog Input PG[8]...
Page 81 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PH[1] Port H GPIO — — DDE3 eMIOS[30] eMIOS Channel FEC_RX_DV Ethernet Receive Data Valid —...
Page 82 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PH12 PH[12] Port H GPIO — — DDE4 eMIOS[19] eMIOS Channel — — — — PH13 PH[13] Port H GPIO...
Page 83 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PJ[6] Port J GPIO — — DDE4 eMIOS[09] eMIOS Channel PCS_D[5] DSPI_D Peripheral Chip Select —...
Page 84 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset Port K (11) PK[0] Port K GPIO — — DDEMLB MLBCLK Media Local Bus Clock SCK_B DSPI_B Serial Clock CLKOUT...
Page 85 Signal Description Table 3-1. PXN20 Signal Properties (continued) Package Pin Status GPIO Locations Supported Volt- (PCR) Description Name Functions Type Type During After Reset Reset PK10 PK[10] Port K GPIO — — DDE2 PCS_B[5] DSPI_B Peripheral Chip Select PCS_D[2] DSPI_D Peripheral Chip Select PCS_A[3] DSPI_A Peripheral Chip Select Miscellaneous Pins (9)
Page 86: I/O Power And Ground Segmentation
Signal Description 3.2.1 I/O Power and Ground Segmentation Table 3-2 gives the preliminary power/ground segmentation. Each segment provides the power and ground for the I/O pins and can be powered by any voltage within the allowed voltage range regardless of the power on the other segments.
Page 87: Pinout
Signal Description Pinout Figure 3-2 shows the 208-ball MAPBGA pin assignments. Figure 3-3 shows the 256-ball MAPBGA pin assignments. For more information, see the PXN20 Microcontroller Data Sheet. PC12 PB13 PB10 RESET XTAL EXTAL DDSYN SSSYN PC11 PC10 PB14 PB11 RCCTL PD14 PC14...
Page 88 Signal Description 256 MAPBGA Ball Map (as viewed from top through the package) PC12 PB13 PB10 RESET XTAL EXTAL DDSYN SSSYN PC11 PC10 PB14 PB11 RCCTL PD14 PC14 PC13 PB15 PB12 PD15 PC15 PA10 PA12 PA14 DDE1 MDO0 PA11 PA15 DDENEX PD10 MDO1...
Page 89: Detailed Signal Description
Signal Description Detailed Signal Description This section provides detailed descriptions of the signal functions available for the device. 3.4.1 Port A Pins 3.4.1.1 PA0 to PA13 — GPI (PA[0:13]) / Analog Input (AN[0:13]) PA[0:13] are general-purpose input (GPI) pins. AN[0:13] are single-ended analog input pins. 3.4.1.2 PA14 —...
Page 90: Pb3 — Gpio (Pb[3]) / Analog Input (An[19]) / Analog Input Channel For External Mux (Anz)
Signal Description 3.4.2.4 PB3 — GPIO (PB[3]) / Analog Input (AN[19]) / Analog Input Channel for External Mux (ANZ) PB[3] is a GPIO pin. AN[19] is a single-ended analog input pin. ANZ is an input channel for the ADC external multiplexer. 3.4.2.5 PB4 to PB7 —...
Page 91: Pb14 — Gpio (Pb[14]) / Analog Input (An[30]) / Dspi_D Peripheral Chip Select (Pcs_D[3])
Signal Description 3.4.2.12 PB14 — GPIO (PB[14]) / Analog Input (AN[30]) / DSPI_D Peripheral Chip Select (PCS_D[3]) PB[14] is a GPIO pin. AN[30] is a single-ended analog input pin. PCS_D[3] is a peripheral chip select output pin for the DSPI D module. 3.4.2.13 PB15 —...
Page 92: Pc8 — Gpio (Pc[8]) / Analog Input (An[40]) / Flexray Debug 2 (Fr_Dbg[2])
Signal Description 3.4.3.8 PC8 — GPIO (PC[8]) / Analog Input (AN[40]) / FlexRay Debug 2 (FR_DBG[2]) PC[8] is a GPIO pin. AN[40] is a single-ended analog input pin. FR_DBG[2] is one of the FlexRay debug output port pins. 3.4.3.9 PC9 — GPIO (PC[9]) / Analog Input (AN[41]) / FlexRay Debug 1 (FR_DBG[1]) PC[9] is a GPIO pin.
Page 93: Port D Pins
Signal Description 3.4.4 Port D Pins 3.4.4.1 PD0 — GPIO (PD[0]) / CAN_A Transmit (CNTX_A) PD[0] is a GPIO pin. CNTX_A is the transmit output pin for the FlexCAN A module. 3.4.4.2 PD1 — GPIO (PD[1]) / CAN_A Receive (CNRX_A) PD[1] is a GPIO pin.
Page 94: Pd12 — Gpio (Pd[12]) / Esci_A Transmit (Txd_A)
Signal Description 3.4.4.10 PD9 — GPIO (PD[9]) / CAN_E Receive (CNRX_E) / RXD_L / I C_C Serial Data Line (SDA_C) PD[9] is a GPIO pin. CNRX_E is the receive input pin for the FlexCAN E module. RXD_L is the receive input pin for the eSCI L module.SDA_C is the serial data line for the I C C module.
Page 95: Pe1 — Gpio (Pe[1]) / Esci_C Receive (Rxd_C) / Emios Channel (Emios[30])
Signal Description 3.4.5.2 PE1 — GPIO (PE[1]) / eSCI_C Receive (RXD_C) / eMIOS Channel (eMIOS[30]) PE[1] is a GPIO pin. RXD_C is the receive input pin for the eSCI C module. eMIOS[30] is an input/output channel pin for the eMIOS200 module. PE[1] can be configured as a wakeup pin in the CRP_PWKENL register.
Page 96: Pe8 — Gpio (Pe[8]) / Esci_G Transmit (Txd_G) / Dspi_A Peripheral Chip Select (Pcs_A[1])
Signal Description 3.4.5.9 PE8 — GPIO (PE[8]) / eSCI_G Transmit (TXD_G) / DSPI_A Peripheral Chip Select (PCS_A[1]) PE[8] is a GPIO pin. TXD_G is the transmit output pin for the eSCI G module. PCS_A[1] is a peripheral chip select output pin for the DSPI A module. 3.4.5.10 PE9 —...
Page 97 Signal Description 3.4.5.16 PE15 — GPIO (PE[15]) / I C_A Serial Data Line (SDA_A) / DSPI_D Peripheral Chip Select (PCS_D[5]) PE[15] is a GPIO pin. SDA_A is the serial data line for the I C A module. PCS_D[5] is a peripheral chip select output pin for the DSPI D module.
Page 98 Signal Description 3.4.6.7 PF6 — GPIO (PF[6]) / DSPI_B Data Input (SIN_B) / DSPI_A Peripheral Chip Select (PCS_A[3]) / DSPI_C Peripheral Chip Select (PCS_C[5]) PF[6] is a GPIO pin. SIN_B is the data input pin for the DSPI B module. PCS_A[3] is a peripheral chip select output pin for the DSPI A module.
Page 99 Signal Description 3.4.6.15 PF14 — GPIO (PF[14]) / DSPI_D Data Input (SIN_D) PF[14] is a GPIO pin. SIN_D is the data input pin for the DSPI D module. 3.4.6.16 PF15 — GPIO (PF[15]) / DSPI_D Peripheral Chip Select (PCS_D[0]) / DSPI_A Peripheral Chip Select (PCS_A[5]) / DSPI_B Peripheral Chip Select (PCS_B[4]) PF[15] is a GPIO pin.
Page 100 Signal Description 3.4.7.6 PG5 — GPIO (PG[5]) / DSPI_D Peripheral Chip Select (PCS_D[4]) / I Serial Data Line (SDA_B) / Analog Input (AN[53]) PG[5] is a GPIO pin. PCS_D[4] is a peripheral chip select output pin for the DSPI D module. SDA_B is the serial data line for the I C_B module.
Page 101 Signal Description 3.4.7.14 PG13 — GPIO (PG[13]) / eMIOS Channel (eMIOS[2]) / Ethernet Transmit Data (FEC_TXD[1]) / Analog Input (AN[61]) PG[13] is a GPIO pin. eMIOS[2] is an input/output channel pin for the eMIOS200 module. FEC_TXD[1] is an Ethernet transmit data output pin. AN[61] is a single-ended analog input pin. 3.4.7.15 PG14 —...
Page 102 Signal Description 3.4.8.5 PH4 — GPIO (PH[4]) / eMIOS Channel (eMIOS[27]) / Ethernet Receive Data (FEC_RXD[0]) PH[4] is a GPIO pin. eMIOS[27] is an input/output channel pin for the eMIOS200 module. FEC_RXD[0] is an Ethernet receive data input pin. 3.4.8.6 PH5 —...
Page 103 Signal Description 3.4.8.15 PH14 — GPIO (PH[14]) / eMIOS Channel (eMIOS[17]) PH[14] is a GPIO pin. eMIOS[17] is an input/output channel pin for the eMIOS200 module. 3.4.8.16 PH15 — GPIO (PH[15]) / eMIOS Channel (eMIOS[16]) PH[15] is a GPIO pin. eMIOS[16] is an input/output channel pin for the eMIOS200 module. 3.4.9 Port J Pins 3.4.9.1...
Page 104 Signal Description 3.4.9.7 PJ6 — GPIO (PJ[6]) / eMIOS Channel (eMIOS[9]) / DSPI_D Peripheral Chip Select (PCS_D[5]) PJ[6] is a GPIO pin. eMIOS[9] is an input/output channel pin for the eMIOS200 module. PCS_D[5] is a peripheral chip select output pin for the DSPI D module. 3.4.9.8 PJ7 —...
Page 105 Signal Description 3.4.9.16 PJ15 — GPIO (PJ[15]) / eMIOS Channel (eMIOS[0]) PJ[15] is a GPIO pin. eMIOS[0] is an input/output channel pin for the eMIOS200 module. 3.4.10 Port K Pins 3.4.10.1 PK0 — GPIO (PK[0]) / Media Local Bus Clock (MLBCLK) / DSPI_B Clock (SCK_B) / Clock Output (CLKOUT) PK[0] is a GPIO pin.
Page 106 Signal Description 3.4.10.6 PK5 — GPIO (PK[5]) / FlexRay Channel A Transmit Enable (FR_A_TX_EN) / External Analog Mux Address Output (MA[2]) / DSPI_C Peripheral Chip Select (PCS_C[3]) PK[5] is a GPIO pin. FR_A_TX_EN in the FlexRay Channel A transmit enable pin. MA[2] is an address output for an external analog multiplexer used to select the multiplexer input channel to connect to the ADC.
Page 107 Signal Description 3.4.10.11 PK10 — GPIO (PK[10]) / DSPI_B Peripheral Chip Select (PCS_B[5]) / DSPI_D Peripheral Chip Select (PCS_D[2]) / DSPI_A Peripheral Chip Select (PCS_A[3]) PK[10] is a GPIO pin. PCS_B[5] is a peripheral chip select output pin for the DSPI A module. PCS_D[2] is a peripheral chip select output pin for the DSPI A module.
Page 108 Signal Description 3.4.11.6 Nexus Message Start/End Out MSEO[1:0] MSEO[1:0] are outputs that indicate when messages start and end on the MDO pins. 3.4.12 Reset and Configuration Signals 3.4.12.1 External Reset Input RESET The RESET pin is a bidirectional I/O pin. It is asserted by an external device to reset the all modules of the device MCU.
Page 109 Signal Description 3.4.14 Clock Synthesizer Signals 3.4.14.1 Crystal Oscillator Input / External Clock Input EXTAL EXTAL is the input pin for an external crystal oscillator or an external clock source. 3.4.14.2 Crystal Oscillator Output XTAL XTAL is the output pin for an external crystal oscillator. 3.4.14.3 System Clock Output CLKOUT...
Page 110 Signal Description 3.4.15.6 Nexus Interface Supply Input DDENEX is the 3.3 V (nominal) supply input for the Nexus Debug Interface. This supply is used only on DDENEX the 256-pin package. 3.4.15.7 Clock Synthesizer Power Input DDSYN is the is the power supply input for the FMPLL. DDSYN 3.4.15.8 Voltage Regulator Control Voltage...
Page 111 Signal Description 3.4.15.15 Clock Synthesizer Ground Input SSSYN is the ground reference input for the FMPLL clock synthesizer. SSSYN NOTE If VDDEMLB is greater than VDD33, then the PK0-2 pins will have extra leakage current if the pin is low (either output drive low, external drive low, or internal pull-down).
Page 112 Signal Description PXN20 Microcontroller Reference Manual, Rev. 1 3-44 Freescale Semiconductor...
Page 113 Chapter 4 Resets Introduction This chapter describes the resets and reset sources for the PXN20. The reset sources supported in the PXN20 are: • Power-on reset (POR) • Low-voltage inhibit (LVI) reset • External reset • Loss-of-lock reset • Loss-of-clock reset •...
Page 114 Resets 4.2.1 Reset (RESET) This pin provides the system reset. It is an open-drain, active-low bidirectional pin. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. Externally asserting the RESET pin resets the chip asynchronously.
Page 115 Resets 4.3.2.2 Low-Voltage Inhibit (LVI) Resets The internal LVI reset signals are asserted when the voltage on the corresponding supply is below defined values. The following are the LVI resets: • LVI12—LVI on internal 1.2 V supply (V • LVI33—LVI on internal 3.3 V supply to I/O pads and flash (V DD33 •...
Page 116 Resets 4.3.2.8 Z0 Core Checkstop Reset When the Z0 core enters a checkstop state, and the checkstop reset is enabled (SIU_SRCR[CRE1] bit), a checkstop reset occurs. The internal reset signal and RESET pin are asserted. The SIU_RSR[CRS] bit is set and all other reset status bits in the SIU_RSR are cleared. 4.3.2.9 JTAG Reset A system reset occurs when JTAG is enabled and the EXTEST, CLAMP, or HIGHZ instruction is executed...
Page 117 Resets 4.4.1 Reset Configuration Timing The timing diagram in Figure 4-1 shows the sampling of the BOOTCFG (PK9) pin for a power-on reset. The timing diagram is also valid for internal/external resets assuming V and V are within valid DD33 operating ranges.
Page 118 Resets PXN20 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 119 Chapter 5 System Clock Description Introduction This chapter describes the clock architecture and sources of the PXN20 system clocks. The PXN20 has a number of different clock sources, serving various application requirements and allowing maximum flexibility for the user application. These are: •...
Page 120 System Clock Description — Clock source from external oscillator — Lock detect circuitry continuously monitors lock status — Loss of clock (LOC) detection for reference and feedback clocks — On-chip loop filter (for improved electromagnetic interference performance and reduces number of external components required) —...
Page 121 System Clock Description TRIMIRC 3.3 V 3.3 or 5 V 4 – 40 3.3 V MHz XTAL EXTAL OSCCLK 16 MHz 3.3 V XTAL SYSCLKSEL 3.3 V Clock OSC32KEN Switcher TRIM128IRC SYSCLKDIV +1,2,4,8,16 1.2 V 32 kHz XTAL EXTAL32 128 kHz 3.3 or 5 V System Clock XTAL32...
Page 122 System Clock Description — jitter < 0.5% — duty cycle: 50% ±10% • Clock source can be kept alive in Sleep mode to facilitate fast start up. However, if > 8 MHz is required, it cannot drive the RTC/API as the output driver needs to be disabled. •...
Page 123 System Clock Description • Powered from internal 1.2 V • Optionally disabled in Sleep mode • Current consumption < 2 µA • 128 kHz ±35% across process, voltage and temperature (before trimming) • 128 kHz ±10% across voltage and temperature (after factory trimming) •...
Page 124 System Clock Description • Because the PXN20 uses a 16 MHz IRC as its default system clock, the FMPLL is put in PLL Off mode during reset, so that power dissipation is minimized by disabling the FMPLL until needed by the system. •...
Page 125 System Clock Description 16_MHZ_IRC System 1 to System clock Core, Clock 16 Platform 4 – 40_MHz_XTAL Selector 2 2 2 FMPLL PLL_Clk 116 MHz Clock Monitor Unit FlexRay Peripheral 1 to 8 Set 1 Peripheral 1 to 8 Set 2 Peripheral 1 to 8 Set 3...
Page 126 System Clock Description ipg_clk_enable ipg_clk Core Logic halt & halt ipg_stop HLTn Halt Idle & control ipg_stop_ack (Tied V HLTACKn MDIS DOZE ips_module_en ipg_clk ipg_clk_s Bus interface (Memory mapped registers) halt ipg_clk Always clocked logic <other>_clk halt (e.g., osc_clk) Protocol interface (e.g., CAN, FlexRay, etc.) Clock gate Figure 5-3.
Page 127 System Clock Description NOTE The CLKOUT provides a nominal 50% duty cycle clock with the exception of the case when the CLKOUT prescaler is equal to ÷ 1 and the system clock and has been divided by its prescaler. When running at this full speed (116 MHz system clock), the CLKOUT should be configured by the user with a divide ratio of at least ÷...
Page 128 System Clock Description Table 5-1. Peripheral Sets Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 Peripheral Set 4 All eSCI modules All FlexCAN modules eMIOS All SPI modules NOTE Unlisted peripherals such as the Flash, SIU, etc., are considered part of the Platform and hence are not listed here.
Page 129 System Clock Description Table 5-2. Software-Controlled Clock Gating Support Block Name Register Name Bit Name DSPI DSPI_MCR MDIS Offset: Base + 0x0000 ESCI ESCIx_CR2 MDIS Offset: Base + 0x0004 FlexCAN CANx_MCR MDIS Offset: Base + 0x0000 EMIOS EMIOS_MCR MDIS Offset: Base + 0x0000 CTUPCR MDIS Offset: Base + 0x00CC...
Page 130 System Clock Description The Z6 and Z0 cores may be idled by their WAIT instructions. The WAIT instructions are used as a power-saving feature to halt the core. Executing the WAIT instruction puts the corresponding core in an idle state at a clean transition point. When the core stops, clocks to the core are gated off, and the core asserts a signal indicating it is waiting for an interrupt.
Page 131 System Clock Description as the clock source for the second domain. Selecting the oscillator as the clock source ensures low jitter on the FlexRay bus. NOTE To prevent improper FlexRay behavior, the system clock or the FlexRay protocol engine clock source must be switched and stable before enabling the FlexRay module.
Page 132 System Clock Description 5.5.4 SWT Clock Domain The clock source for the SWT is the 16 MHz_IRC. 5.5.5 Input/Output Processor (IOP) Clocking The e200z0 IOP always runs at half the system frequency. If the system frequency source is the 16 MHz_IRC (e.g. after wake-up) the IOP is clocked at 8 MHz. 5.5.6 FEC Clocking The Fast Ethernet Controller is not capable of running at the target system bus speed of the device.
Page 133 Chapter 6 Clocks, Reset, and Power (CRP) Introduction The primary function of the clock, reset, and power (CRP) block is to maintain all of the control logic that requires power when other portions of the device are powered down in power-saving modes. The CRP manages entry into, operation during, and exit from power-saving modes.
Page 134 Clocks, Reset, and Power (CRP) 4 – 40 MHz XTAL 32 kHz XTAL 128 kHz 16 MHz POWER CLOCKS, RESET CONTROL WAKEUP, POWER STATUS RTC / INPUT ISOLATION POWER ISOLATION SWITCHES LOGIC VREG CLOCK SYSTEM FMPLL CONTROL CLOCK SEA-OF-GATES BLOCK LOGIC BLOCKS Figure 6-1.
Page 135 Clocks, Reset, and Power (CRP) — Four selectable counter clock sources – 4 – 40 MHz XTAL with 1 to 16 divider – 32 kHz XTAL – 16 MHz_IRC with 1 to 16 divider stage – 128 kHz_IRC with 1 to 4 divider stage —...
Page 136 Clocks, Reset, and Power (CRP) 6.1.3 Modes of Operation There are two functional modes of operation for the CRP: normal operation and sleep mode. In normal operation, all CRP registers can be read or written. The input isolation, low-power FSM, and wake-up logic are disabled.
Page 137 Clocks, Reset, and Power (CRP) Table 6-1. CRP Memory Map (continued) Offset from CRP_BASE Register Access Reset Value Section/Page (0xFFFE_C000) 0x0070 CRP_SOCSC—SoC status and control register 0x4000_0000 6.2.2.12/6-15 0x0074–0x03FF Reserved 6.2.2 Register Descriptions This section lists the CRP registers in address order and describes the registers and their bit fields. 6.2.2.1 Clock Source Register (CRP_CLKSRC) The CRP_CLKSRC contains:...
Page 138 Clocks, Reset, and Power (CRP) Table 6-2. CRP_CLKSRC Field Descriptions (continued) Field Description EN128KIRC Enable 128 kHz IRC Oscillator. The EN128KIRCbit enables the 128 kHz IRC oscillator. 0 128 kHz IRC disabled. 1 128 kHz IRC enabled. Note: After enabling the128 kHz IRC, software needs to wait the required crystal startup/stabilization time before making use of this oscillator.
Page 139 Clocks, Reset, and Power (CRP) Offset: CRP_BASE + 0x0010 Access: User read/write R CNTE FRZE RTCIE ROVREN RTCVAL Reset APIEN APIIE CLKSEL DIV512EN DIV32EN APIVAL Reset These bits are only reset by power-on: VDD15 LVI, VDD33 LVI, and VDDSYN LVI, VDD5 low LVI, and VDD5 LVI. Figure 6-3.
Page 140 Clocks, Reset, and Power (CRP) Table 6-3. CRP_RTCC Field Descriptions (continued) Field Description CLKSEL Clock Select. The CLKSEL bits select the clock source for the RTC. CLKSEL should only be updated when CNTEN is 0. The user should ensure that oscillator is enabled before selecting it as a clock source for RTC. 00 32 kHz OSC 01 128 kHz IRC 10 16 MHz IRC...
Page 141 Clocks, Reset, and Power (CRP) Table 6-4. CRP_RTSC Field Descriptions Field Description RTCF RTC Interrupt Flag. The RTCF bit indicates that the RTC counter has reached the counter value matching RTCVAL. RTCF is cleared by writing a 1 to RTCF. Writing a 0 to RTCF has no effect. Note that the RTCF bit must be cleared before entering sleep mode, if the RTC is to be used as the wakeup source.
Page 142 Clocks, Reset, and Power (CRP) Offset: CRP_BASE + 0x0040 Access: User read/write PWK31 PWK30 PWK29 PWK28 PWK27 PWK26 PWK25 PWK24 Reset PWK23 PWK22 PWK21 PWK20 PWK19 PWK18 PWK17 PWK16 Reset Figure 6-6. Pin Wakeup Enable High Register (CRP_PWKENH) Offset: CRP_BASE + 0x0044 Access: User read/write PWK15 PWK14...
Page 143 Clocks, Reset, and Power (CRP) Table 6-7. Wakeup Source Number vs. Pin (continued) CRP_PWKENL CRP_PWKENH PWKn PWKn PWKn PWKn PF11 PJ14 PF15 NOTE Program any pins that are to be used as wakeup sources as inputs in the associated SIU_PCRn register prior to entering a low-power mode. 6.2.2.6 Pin Wakeup Source Interrupt Enable Register (CRP_PWKSRCIE) The CRP_PWKSRCIE register enables interrupt requests individually for each of the pin wakeup sources.
Page 144 Clocks, Reset, and Power (CRP) Table 6-9. CRP_PWKSRCF Field Descriptions Field Description PWKSRCFn Pin Wakeup Source Flag. The PWKSRCF bits indicate which external pin wakeup source event caused the wakeup. More than one external wakeup source can be asserted at a time if the wakeup events happened simultaneously.
Page 145 Clocks, Reset, and Power (CRP) • Recovery vector for the Z0 core • Reset for the Z0 core Offset: CRP_BASE + 0x0054 Access: User read/write 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Z0VEC Z0RST Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...
Page 146 Clocks, Reset, and Power (CRP) Table 6-12. CRP_RECPTR Field Descriptions Field Description RECPTR Recovery Pointer. The RECPTR value is a generic 30-bit register available to the user application which retains a value during all low-power modes. This register may be used by the user software to indicate where in RAM a recovery routine exists.
Page 147 Clocks, Reset, and Power (CRP) Table 6-13. CRP_PSCR Field Descriptions (continued) Field Description RTCWKF RTC Wakeup Flag. The RTCWKF bit indicates that the RTC match was the wakeup source. A write of 1 clears the interrupt flag and a write of 0 has no effect. 0 The RTC did not cause the last wakeup.
Page 148 Clocks, Reset, and Power (CRP) • LVI reset enables • LVI lock bit Offset: CRP_BASE + 0x0070 Access: User read/write R LVI5 LVI5 LVI5H LVI5N LVI5 FRIE FDIS LOCK Reset LVI5HIF LVI5NF LVI5F FRF FRDY Reset These bits are only reset by power on, VDD15 LVI, VDD33 LVI, VDDSYN LVI, and VDD5 Low LVI. Figure 6-14.
Page 149 Clocks, Reset, and Power (CRP) Table 6-14. CRP_SOCSC Field Descriptions (continued) Field Description LVI5HF LVI 5V High Interrupt Flag. The LVI5HF bit indicates that the LVI5H LVI circuit has detected that the 5V supply is below the trip limit. LVI5HF is cleared by writing a 1 to LVI5HF. Writing a 0 to LVI5HF has no effect. 0 No LVI5H interrupt.
Page 150 Clocks, Reset, and Power (CRP) interrupt when the device wakes up. Each external wake-up has individual wakeup flag and interrupt enable and are grouped together into one interrupt vector. Refer to Chapter 3, Signal Description, details on the allocation of pins to the Wake-up lines. In order to minimize spurious wake-up as a result of noise, fixed duration input filters are applied to every wake-up pin.These filters are based on either the 128 kHz or 16 MHz clock sources and use 2 clock cycles to synchronize the input wake-up signal.
Page 151 Clocks, Reset, and Power (CRP) 6.3.3.2 Sleep Mode RAM Retention The RAMSEL bits in the CRP_PSCR register determine the amount of RAM that remains powered in sleep mode. This selection must be made prior to executing the WAIT instructions to the cores with the CRP_PSCR[SLEEP] bit set.
Page 152 Clocks, Reset, and Power (CRP) INIT Assert clock stop Sleep (Run Mode) to clock control block Request debug enabled? Set Sleep Handshake Handshake bit bit cleared? in NPC PCR wait 5 clks - Acknowledge clock stop ready to CCB Mode Transition: RUN SLEEP - Assert TDO OBE 3 clks...
Page 153 Clocks, Reset, and Power (CRP) Mode Transition: SLEEP - Enable isolation for mem/analog blks - Isolate CRP block From Figure 6-15 - Assert system POR - Safe state pads - RAMs in standby - Bias resistor on -Negate run - Negate prerun (pgates) (pgates) - RAMs sbias...
Page 154 Clocks, Reset, and Power (CRP) Mode Transition: SLEEP State 16 - Negate system POR Figure 6-16 - Bias resistor off Debug Enabled? - Block NPC debug signals - dbg clk = 16 MHz_IRC - Assert core debug enable - Device exits SLEEP - Un-latch NPC wait core dbg ack debug signals...
Page 155 Clocks, Reset, and Power (CRP) 6.3.4.1 Sleep Mode Reset Operation The reset controller in the SIU controls the normal reset sequences from POR, LVI, and other resets when the device is in RUN mode. The CRP controls reset operation for the device in sleep mode. The external RESET pin is enabled in all modes.
Page 156 Clocks, Reset, and Power (CRP) The corresponding CRP_PSCR[PWKSRCF] flag bit is set when a selected and enabled event occurs on an external pin wakeup source. An interrupt request can be generated for an external pin wakeup by setting the corresponding CRP_PSCR[PWKSRIE] bit. This interrupt request is pending once the device recovers from the previous low-power mode.
Page 157 Clocks, Reset, and Power (CRP) NOTE TDO is pulled high on entry into low power mode. It is driven low when the MCU wakes up. The assertion of the TDO pin indicates to the debug tool that it can now restore the debug register contents via the JTAG interface.
Page 158 Clocks, Reset, and Power (CRP) The RTC also supports an autonomous periodic interrupt function used to generate a periodic wakeup request to exit sleep mode or an interrupt request. 6.4.1 RTC Features Features of the RTC include: • 32-bit counter •...
Page 159 Clocks, Reset, and Power (CRP) the 32 kHz OSC must be enabled before being selected. The 32 kHz OSC is selected to give a more accurate wakeup than the 128 kHz IRC. (CNTEN must be disabled when the clock sources are switched.) When the counter value for counter bits 10–21 match the 12-bit value in RTCVAL, then the RTCF interrupt flag is set (after proper clock synchronization).
Page 160 Clocks, Reset, and Power (CRP) RTCCNT APIF API Interrupt APIIE sync APIVAL 9–0 sync CLKSEL APIEN 512 offset reg load reset CNTEN DIV512EN 9–0  32 API Wakeup DIV32EN 32-bit counter reset 21–10 RTCVAL RTC Wakeup RTC Rollover Wakeup sync sync ROVREN RTC cnt_or_rlovr...
Page 161 Clocks, Reset, and Power (CRP) Power Supply Monitors 6.5.1 Power-On Reset (POR) The internal Power On Reset (POR) monitors the main supply input voltage (V ) and shall not release the internal reset line until V is above the de-assertion threshold. The POR is always enabled. 6.5.2 Low-Voltage Monitors (LVI) The internal LVI circuits monitor when the voltage on the corresponding supply is lower than defined...
Page 162 Clocks, Reset, and Power (CRP) PXN20 Microcontroller Reference Manual, Rev. 1 6-30 Freescale Semiconductor...
Page 163 Chapter 7 Frequency Modulated Phase-Locked Loop (FMPLL) Introduction The frequency modulated phase-locked loop (FMPLL) module is a frequency modulated phase-locked loop that has been optimized to generate voltage controlled oscillator (VCO) frequencies from 192 MHz – 600 MHz based on an input clock range of 4 MHz to 40 MHz. The frequency multiplication, output dividers and the frequency modulation waveform are register-programmable through a peripheral bus interface.
Page 164 Frequency Modulated Phase-Locked Loop (FMPLL) • Because the PXN20 uses a 16 MHz IRC as its default system clock, the FMPLL is put in PLL Off mode during reset, so that power dissipation is minimized by disabling the FMPLL until needed by the system.
Page 165 Frequency Modulated Phase-Locked Loop (FMPLL) Table 7-1. FMPLL Memory Map Offset from FMPLL_BASE_ADDR Register Access Reset Value Section/Page (0xFFFF_0000) 0x0000 Reserved 0x0004 SYNSR—FMPLL synthesizer status register 0x0000_0000 7.3.2.1/7-3 0x0008 ESYNCR1—FMPLL enhanced synthesizer control register 1 0x8000_0030 7.3.2.2/7-5 0x000C ESYNCR2—FMPLL enhanced synthesizer control register 2 0x0000_0003 7.3.2.3/7-7 0x0010–0x0014...
Page 166 Frequency Modulated Phase-Locked Loop (FMPLL) Table 7-2. SYNSR Register Field Descriptions (continued) Field Description Loss-Of-Clock Status. The LOC bit is an indication of whether a loss-of-clock condition is present when operating in normal PLL mode. If LOC = 0, the system clocks are operating normally. If LOC = 1, the system clocks have failed due to a reference failure or a PLL failure.
Page 167 Frequency Modulated Phase-Locked Loop (FMPLL) Table 7-2. SYNSR Register Field Descriptions (continued) Field Description CALDONE Calibration Complete. The CALDONE bit is an indication of whether the calibration sequence has been completed since the last time modulation was enabled. If CALDONE = 0 then the calibration sequence is in progress or modulation is disabled.
Page 168 Frequency Modulated Phase-Locked Loop (FMPLL) Offset: FMPLL_BASE_ADDR + 0x0008 Access: User read/write CLKCFG[0:2] EPREDIV Reset EMFD Reset Figure 7-3. FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1) Table 7-4. ESYNCR1 Register Field Descriptions Field Description bit 0 Reserved. Note: This bit is set to 1 on reset and always reads as 1. CLKCFG Clock Configuration.
Page 169 Frequency Modulated Phase-Locked Loop (FMPLL) Table 7-5. Pre-divider Ratios EPREDIV Input Divide Ratio (EPREDIV+1) 0000 1 (default for PXN20) 0001 0010 0011 0100 0101 0110 Invalid 0111 1000 Invalid 1001 1010–1111 Invalid Table 7-6. Feedback Divide Ratios EMFD Feedback Divide Ratio (EMFD+16) 0000_0000–0001_1111 Invalid 0010_0000...
Page 170 Frequency Modulated Phase-Locked Loop (FMPLL) Offset: FMPLL_BASE_ADDR + 0x000C Access: User read/write LOCEN LOLRE LOCRE ERATE Reset EDEPTH ERFD Reset Figure 7-4. FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2) Table 7-7. ESYNCR2 Field Descriptions Field Description LOCEN Loss-of-Clock Enable. The LOCEN bit determines whether the loss-of-clock function is operational along with backup clock modes, and interrupt and reset functions.
Page 171 Frequency Modulated Phase-Locked Loop (FMPLL) Table 7-7. ESYNCR2 Field Descriptions (continued) Field Description ERATE Enhanced Modulation Rate. The ERATE bits control the rate of frequency modulation applied to the system frequency. Table 7-8 shows the allowable modulation rates. Note: The PLL modulation rate must be within the f specification (see the PXN20 Microcontroller Data Sheet).
Page 172 Frequency Modulated Phase-Locked Loop (FMPLL) Table 7-10. Output Divide Ratios ERFD Output Divide Ratio (ERFD+1) 00_0000 00_0001 00_0010 Invalid 00_0011 4 (default value for PXN20) 00_0100 Invalid 00_0101 00_0110 Invalid 00_0111 11_1100 Invalid 11_1101 11_1110 Invalid 11_1111 Functional Description The FMPLL module contains the frequency modulated phase lock loop (FMPLL), enhanced frequency divider (ERFD), enhanced synthesizer control registers (ESYNCR1 and ESYNCR2), synthesizer status register (SYNSR), and clock/PLL control logic.
Page 173 Frequency Modulated Phase-Locked Loop (FMPLL) 7.4.2 PLL Off Mode When PLL Off mode is selected, the PLL is turned off. Either the 16 MHz IRC must be selected as the system clock, or the user must supply an external clock or crystal on the EXTAL pin and select that clock source before entering PLL off mode.
Page 174 Frequency Modulated Phase-Locked Loop (FMPLL) Continue Feedback count does not monitoring PLL equal reference count of N or with alternate N+K. Alert system that PLL N and N+K count Alert system that is not locked. Tighten and compare PLL has locked. lock criteria.
Page 175 Frequency Modulated Phase-Locked Loop (FMPLL) caused by a reference clock failure or a PLL failure. If the reference fails, the PLL goes out of lock and into self-clocked mode (SCM) (see Table 7-12). The PLL remains in SCM until the next reset. When the PLL is operating in SCM, the PLL runs open loop at a default VCO frequency.
Page 176 Frequency Modulated Phase-Locked Loop (FMPLL) much the two clocks lead or lag each other. After phase lock is achieved, the PFD continues to pulse the UP and DOWN signals for a very short duration during each reference clock cycle. These short pulses force the PLL to continually update and prevent a frequency drift phenomena referred to as “dead-banding.”...
Page 177 Frequency Modulated Phase-Locked Loop (FMPLL) 2. Write a value of ERFD = ERFD (from step 1) + 1 to the ERFD field of the ESYNCR2. Not increasing the ERFD when changing the EPREDIV or EMFD could subject the device to clock frequencies beyond the range specified for the device due to the PLL’s unlocked state.
Page 178 Frequency Modulated Phase-Locked Loop (FMPLL) Fm Fm t --------------- - F mod + {0.5%, 1%, 1.5%, 2%} – {0.5%, 1%,1.5%, 2%} /Q where Q = {20, 40, 80} extal Figure 7-6. Frequency Modulation Waveform 7.4.3.4.1 Frequency Modulation Depth Calibration The frequency modulation calibration system tunes a reference current into the modulation D/A so that the modulation depth (F and F ) remains within specification.
Page 179 Frequency Modulated Phase-Locked Loop (FMPLL) cycles again to obtain the delta-frequency count. The counter runs only during the high phase of the triangular modulation waveform. Several half-modulation periods are measured during the calibration routine to increase the resolution of the frequency measurement. This results in a measurement of the average frequency during the high phase of the modulation waveform, which under ideal circumstances is equivalent to one-half of the desired modulation depth.
Page 180 Frequency Modulated Phase-Locked Loop (FMPLL) Resets This section describes the reset operation of the PLL, including power-on reset and normal resets. The reset values of registers and signals are provided in other sections. 7.5.1 Clock Mode Selection The initial clock mode is reflected in the MODE, PLLSEL, and PLLREF bits of the synthesizer status register (SYNSR) as well as the ESYNCR1[CLKCFG] bit field.
Page 181 Frequency Modulated Phase-Locked Loop (FMPLL) CAUTION When running in an unlocked state, the clocks generated by the PLL are not guaranteed stable and may exceed the maximum specified operating frequency of the device. The RFD should always be used as described in Section 7.4.3.3.5, Programming System Clock Frequency, to insulate the system from any potential frequency overshoot of the PLL clocks.
Page 182 Frequency Modulated Phase-Locked Loop (FMPLL) PXN20 Microcontroller Reference Manual, Rev. 1 7-20 Freescale Semiconductor...
Page 183 Chapter 8 System Integration Unit (SIU) Introduction The system integration unit (SIU) controls MCU reset configuration, the system reset operation, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, clock frequency divider configuration, peripheral clock disable configuration, and peripheral clock disable acknowledge.
Page 184 System Integration Unit (SIU) Pad Configuration • • • Power-on Reset Reset RESET Controller Detection PC5 (NMI[0] Z6) External IRQ/ • • • • PC6 (NMI[1] Z0) Edge • • Detects & Registers Control Interface/ PK9 (BOOTCFG) Ring Reset Configuration PA[0:15] •...
Page 185 System Integration Unit (SIU) — Power-on reset support — Reset status register providing last reset source to software — Software controlled reset assertion • External interrupt — 16 interrupt requests (139 inputs multiplexed down to 16 inputs in eight groups of 16 and one group of 11, on Ports A through K) —...
Page 186 System Integration Unit (SIU) 8.2.1 Ports vs. General-Purpose I/O Pins The PXN20 provides 155 individual GPIO pins, organized into 10 ports named Port A through Port K. Port I is omitted from the series of ports. Of these ports, Ports A through J provide 16 pins each, and Port K provides 11 pins.
Page 187 System Integration Unit (SIU) Table 8-1. SIU Memory Map (continued) Offset from SIU_BASE Register Access Reset Value Section/Page (0xFFFE_8000) 0x002C SIU_IFEER—External IRQ falling-edge event enable register 0x0000_0000 8.3.2.10/8-20 0x0030 SIU_IDFR—External IRQ digital filter register 0x0000_0000 8.3.2.11/8-21 0x0034 SIU_IFIR—External IRQ filtered input register 0x0000_0000 8.3.2.12/8-22 0x0038–0x003F Reserved...
Page 188 System Integration Unit (SIU) Table 8-1. SIU Memory Map (continued) Offset from SIU_BASE Register Access Reset Value Section/Page (0xFFFE_8000) 0x09C0 SIU_EMIOS_SEL3—eMIOS select register 3 0x0000_0000 8.3.2.25/8-44 0x09C4 SIU_ISEL2A—External interrupt select register 2A 0x0000_0000 8.3.2.26/8-45 0x09C8–0x0BFF Reserved 0x0C00 SIU_PGPDO0—Parallel GPIO pin data output register 0 0x0000_0000 8.3.2.27/8-48 0x0C04...
Page 189 System Integration Unit (SIU) Table 8-1. SIU Memory Map (continued) Offset from SIU_BASE Register Access Reset Value Section/Page (0xFFFE_8000) 0x0D18 SIU_DSPIDH—Masked serial GPO register for DSPI_D high 0x0000_0000 8.3.2.52/8-61 0x0D1C SIU_DSPIDL—Masked serial GPO register for DSPI_D low 0x0000_0000 8.3.2.53/8-62 0x0D20–0x0D43 Reserved 0x0D44 SIU_EMIOSA—eMIOS select register for DSPI_A 0x0000_0000...
Page 190 System Integration Unit (SIU) Table 8-2. Detailed Memory Map for SIU_PCR, SIU_GPDO, and SIU_GPDI SIU_PCR SIU_GPDO SIU_GPDI Pad ID Pad # Address Address Address FFFE_8040 PA[15:0] FFFE_8800 FFFE_8042 FFFE_8801 inputs only FFFE_8044 FFFE_8802 FFFE_8046 FFFE_8803 FFFE_8048 FFFE_8804 FFFE_804A FFFE_8805 FFFE_804C FFFE_8806 FFFE_804E FFFE_8807...
Page 191 System Integration Unit (SIU) Table 8-2. Detailed Memory Map for SIU_PCR, SIU_GPDO, and SIU_GPDI (continued) SIU_PCR SIU_GPDO SIU_GPDI Pad ID Pad # Address Address Address FFFE_8080 FFFE_8620 FFFE_8820 FFFE_8082 FFFE_8621 FFFE_8821 FFFE_8084 FFFE_8622 FFFE_8822 FFFE_8086 FFFE_8623 FFFE_8823 FFFE_8088 FFFE_8624 FFFE_8824 FFFE_808A FFFE_8625 FFFE_8825...
Page 192 System Integration Unit (SIU) Table 8-2. Detailed Memory Map for SIU_PCR, SIU_GPDO, and SIU_GPDI (continued) SIU_PCR SIU_GPDO SIU_GPDI Pad ID Pad # Address Address Address FFFE_80C0 FFFE_8640 FFFE_8840 FFFE_80C2 FFFE_8641 FFFE_8841 FFFE_80C4 FFFE_8642 FFFE_8842 FFFE_80C6 FFFE_8643 FFFE_8843 FFFE_80C8 FFFE_8644 FFFE_8844 FFFE_80CA FFFE_8645 FFFE_8845...
Page 193 System Integration Unit (SIU) Table 8-2. Detailed Memory Map for SIU_PCR, SIU_GPDO, and SIU_GPDI (continued) SIU_PCR SIU_GPDO SIU_GPDI Pad ID Pad # Address Address Address FFFE_8100 FFFE_8660 FFFE_8860 FFFE_8102 FFFE_8661 FFFE_8861 FFFE_8104 FFFE_8662 FFFE_8862 FFFE_8106 FFFE_8663 FFFE_8863 FFFE_8108 FFFE_8664 FFFE_8864 FFFE_810A FFFE_8665 FFFE_8865...
Page 194 System Integration Unit (SIU) Table 8-2. Detailed Memory Map for SIU_PCR, SIU_GPDO, and SIU_GPDI (continued) SIU_PCR SIU_GPDO SIU_GPDI Pad ID Pad # Address Address Address FFFE_8140 FFFE_8680 FFFE_8880 FFFE_8142 FFFE_8681 FFFE_8881 FFFE_8144 FFFE_8682 FFFE_8882 FFFE_8146 FFFE_8683 FFFE_8883 FFFE_8148 FFFE_8684 FFFE_8884 FFFE_814A FFFE_8685 FFFE_8885...
Page 195 System Integration Unit (SIU) 8.3.2 Register Descriptions This section lists the DSPI registers in address order and describes the registers and their bit fields. 8.3.2.1 MCU ID Register (SIU_MIDR) The SIU_MIDR contains the part identification number, package type, and mask revision number specific to the device.
Page 196 System Integration Unit (SIU) 8.3.2.2 Reset Status Register (SIU_RSR) The SIU_RSR reflects the most recent source, or reset sources, and the pins’ configuration state at reset. This register contains one bit for each reset source, indicating the last reset was power-on reset (POR), external, software system, watchdog, loss of PLL lock, loss of clock, or checkstop reset.
Page 197 System Integration Unit (SIU) Table 8-5. SIU_RSR Field Descriptions Field Description PORS Power-on Reset Status. Set for any power-on or LVI reset. Also set on recovery from sleep mode. 0 The reset controller acknowledged another reset source since the last assertion of the power-on reset input. 1 The power-on reset input to the reset controller is asserted, and no other reset source has been acknowledged since that assertion of the power-on reset input except an external reset.
Page 198 System Integration Unit (SIU) Table 8-6. SIU_SRCR Field Descriptions Field Description Software System Reset. Used to generate a software system reset. Writing a 1 to this bit causes an internal reset. The software system reset is processed as a synchronous reset. The bit is automatically cleared on the assertion of any other reset source except a software external reset.
Page 199 System Integration Unit (SIU) Offset: SIU_BASE + 0x0014 Access: User read/write NMI0 NMI1 Reset w1c Reset w1c Figure 8-5. SIU External Interrupt Status Register (SIU_EISR) Table 8-7. SIU_EISR Field Descriptions Field Description NMI0 Non-Maskable Interrupt Flag for primary CPU (Z6). NMI0 is for the primary core. This bit is set when an edge-triggered event occurs on the corresponding NMI0 input.
Page 200 System Integration Unit (SIU) Offset: SIU_BASE + 0x0018 Access: User read/write Reset R EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE Reset Figure 8-6. SIU DMA/Interrupt Request Enable Register (SIU_DIRER) Table 8-8. SIU_DIRER Field Descriptions Field Description EIREn...
Page 201 System Integration Unit (SIU) 8.3.2.7 Overrun Status Register (SIU_OSR) The SIU_OSR contains flag bits that record an overrun. These flag bits are cleared by writing 1 to the bits (w1c); writing 0 has no effect. Offset: SIU_BASE + 0x0020 Access: User read/write Reset R OVF Reset w1c...
Page 202 System Integration Unit (SIU) Table 8-11. SIU_ORER Field Descriptions Field Function OREn Overrun Request Enable n. Enables the corresponding overrun request when an overrun occurs on the corresponding IRQn pin. 0 Overrun request disabled. 1 Overrun request enabled. 8.3.2.9 IRQ Rising-Edge Event Enable Register (SIU_IREER) The SIU_IREER allows rising-edge-triggered events to be enabled on the corresponding IRQn pins.
Page 203 System Integration Unit (SIU) Offset: SIU_BASE + 0x002C Access: User read/write NFEE0 NFEE1 Reset R IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE Reset Once written, the NFEEn bits cannot be changed until the next reset. Figure 8-11.
Page 204 System Integration Unit (SIU) Table 8-14. SIU_IDFR Field Descriptions Field Function Digital Filter Length. Defines digital filter period on the IRQn inputs according to the following equation:     ystemClockPeriod  Filter Period SystemClockPeriod For a 116 MHz system clock, this gives a range of 15.6 ns to 256 s. The minimum time of two clocks accounts for synchronization of the IRQ input pins with the system clock.
Page 205 System Integration Unit (SIU) • If the pin is configured as an input, the ODE and SRC bits do not apply. • If the pin is configured as an output, the HYS bit does not apply. • When a pin is configured as an output, the weak internal pull up/down is disabled, regardless of the WPE or WPS settings in the SIU_PCR.
Page 206 System Integration Unit (SIU) Table 8-16. SIU_PCR Field Descriptions Field Description Pin Assignment. Selects a multiplexed pad function. A separate port enable output signal from the SIU is asserted for each register value. PA Field Pin Function 0b00 GPIO 0b01 Function 1 0b10 Function 2...
Page 207 System Integration Unit (SIU) Table 8-16. SIU_PCR Field Descriptions (continued) Field Description Slew Rate Control. Controls slew rate for the pad. Slew rate control pertains to pins with slow or medium I/O pad types, and the output signals are driven according to the value of this field. Actual slew rate is dependent on the pad type and load.
Page 208 System Integration Unit (SIU) Section 8.3.2.13.3, Pad Configuration Registers 144–146 (SIU_PCR144–SIU_PCR146). For each pin, Table 3-1 lists the signals that are available as the PA settings for Function1, Function2, and Function3. Offset: SIU_BASE+0x0060–SIU_BASE+0x015E; SIU_BASE+0x0166–SIU_BASE+0x0174 Access: User read/write WPE WPS Reset The reset value is 1 for SIU_PCR153 (BOOTCFG), 0 for all other SIU_PCRs in this range.
Page 209 System Integration Unit (SIU) Offset: SIU_BASE + 0x0610–SIU_BASE+0x0698 Access: User read/write Reset Reset Figure 8-17. GPIO Pin Data Out Register 16–19 (SIU_GPDO16_19) Table 8-17. SIU_GPDOn Field Descriptions Field Description PDOn Pin Data Out. Stores the data to be driven out on the external GPIO pin associated with the register.
Page 210 System Integration Unit (SIU) Table 8-18. Pin Data Output Register to Pin Mapping (continued) SIU_GPDOn Address Offset Pins 112_115 0x0670 PH0–PH3 116_119 0x0674 PH4–PH7 120_123 0x0678 PH8–PH11 124_127 0x067C PH12–PH15 128_131 0x0680 PJ0–PJ3 132_135 0x0684 PJ4–PJ7 136_139 0x0688 PJ8–PJ11 140_143 0x068C PJ12–PJ15 144_147...
Page 211 System Integration Unit (SIU) Table 8-20. GPIO Pin Data Input Register to Pin Mapping SIU_GPDIn Address Offset Pins 0x0800 PA0–PA3 0x0804 PA4–PA7 8_11 0x0808 PA8–PA11 12_15 0x080C PA12–PA15 16_19 0x0810 PB0–PB3 20_23 0x0814 PB4–PB7 24_27 0x0818 PB8–PB11 28_31 0x081C PB12–PB15 32_35 0x0820 PC0–PC3...
Page 212 System Integration Unit (SIU) Offset: SIU_BASE + 0x0904 Access: User read/write ESEL15 ESEL14 ESEL13 ESEL12 ESEL11 ESEL10 ESEL9 ESEL8 Reset ESEL7 ESEL6 ESEL5 ESEL4 ESEL3 ESEL2 ESEL1 ESEL0 Reset Figure 8-19. IMUX Select Register 1 (SIU_ISEL1) Table 8-21. SIU_ISEL1 Field Descriptions Field Description ESEL15...
Page 213 System Integration Unit (SIU) Table 8-21. SIU_ISEL1 Field Descriptions (continued) Field Description ESEL9 External IRQ Input Select 9. Specifies input for IRQ9. 00 PB9 pin. 01 PC9 pin. 10 PD9 pin. 11 ISEL2. ESEL8 External IRQ Input Select 8. Specifies input for IRQ8. 00 PB8 pin.
Page 214 System Integration Unit (SIU) Table 8-21. SIU_ISEL1 Field Descriptions (continued) Field Description ESEL1 External IRQ Input Select 1. Specifies input for IRQ1. 00 PB1 pin. 01 PC1 pin. 10 PD1 pin. 11 ISEL2. ESEL0 External IRQ Input Select 0. Specifies input for IRQ0. 00 PB0 pin.
Page 215 System Integration Unit (SIU) 8.3.2.17 IMUX Select Register 2 (SIU_ISEL2) The SIU_ISEL2 register selects the source for the external interrupt. The selection is made in conjunction with SIU_ISEL1 and SIU_ISEL2A. Figure 8-72 shows how ISEL1, ISEL2, and ISEL2A interact. Offset: SIU_BASE + 0x0908 Access: User read/write ESEL15...
Page 216 System Integration Unit (SIU) Table 8-22. SIU_ISEL2 Field Descriptions (continued) Field Description ESEL9 External IRQ Input Select 9. Specifies input for IRQ9. 00 PE9 pin. 01 PF9 pin. 10 PG9 pin. 11 ISEL2A. ESEL8 External IRQ Input Select 8. Specifies input for IRQ8. 00 PE8 pin.
Page 217 System Integration Unit (SIU) Table 8-22. SIU_ISEL2 Field Descriptions (continued) Field Description ESEL1 External IRQ Input Select 1. Specifies input for IRQ1. 00 PE1 pin. 01 PF1 pin. 10 PG1 pin. 11 ISEL2A. ESEL0 External IRQ Input Select 0. Specifies input for IRQ0. 00 PE0 pin.
Page 218 System Integration Unit (SIU) 8.3.2.19 Chip Configuration Register (SIU_CCR) Offset: SIU_BASE + 0x0980 Access: User read-only MATCH DISNEX Reset TEST LOCK Reset Writes to this bit have no effect, but reads return the written value. Reserved, do not write. Figure 8-22. Chip Configuration Register (SIU_CCR) Table 8-24.
Page 219 System Integration Unit (SIU) 8.3.2.20 External Clock Control Register (SIU_ECCR) The SIU_ECCR controls the timing relationship between the system clock and the external clocks, CLKOUT. All bits and fields in the SIU_ECCR are read/write and reset by the asynchronous reset signal. Offset: SIU_BASE + 0x0984 Access: User read-only...
Page 220 System Integration Unit (SIU) 8.3.2.21 General Purpose Register 0–3 (SIU_GPRn) The SIU_GPRn registers provide general-purpose read/write registers for customer use. Offset: SIU_BASE + 0x0988 (SIU_GPR0) 0x0990 (SIU_GPR2) 0x098C (SIU_GPR1) 0x0994 (SIU_GPR3) Access: User read/write Reset Reset Figure 8-24. General Purpose Register 0–3 (SIU_GPRn) 8.3.2.22 System Clock Register (SIU_SYSCLK) The SIU_SYSCLK register controls the source for the system clock, the divider for the system clock, and...
Page 221 System Integration Unit (SIU) Table 8-26. SIU_SYSCLK Field Descriptions Field Description SYSCLKSEL System Clock Select. The SYSCLKSEL bit selects the source for the system clock. 00 System clock supplied by 16 MHz IRC. 01 System clock supplied by 4 – 40 MHz_XTAL. 10 System clock supplied by FMPLL.
Page 222 System Integration Unit (SIU) Offset: SIU_BASE + 0x09A4 Access: User read-only Reset R HLT Reset Writes to this bit are reflected in the SIU_HLT0 and SIU_HLTACK0 register, but have no other effect. Figure 8-26. Halt Register 0 (SIU_HLT0) Table 8-27. SIU_HLT0 Register Field Descriptions Field Description HLT6...
Page 223 System Integration Unit (SIU) Offset: SIU_BASE + 0x09A8 Access: User read-only Reset Reset Reserved, do not write to this bit. Writes to this bit are reflected in the SIU_HLT1 and SIU_HLTACK1 register, but have no other effect. Figure 8-27. Halt Register 1 (SIU_HLT1) Table 8-28.
Page 224 System Integration Unit (SIU) Offset: SIU_BASE + 0x09AC Access: User read-only Reset R HLT Reset Setting the corresponding bit in SIU_HLT0 sets this bit, but has no other effect. Figure 8-28. Halt Acknowledge Register 0 (SIU_HLTACK0) Table 8-29. SIU_HLTACK0 Register Field Descriptions Field Description HLTACK6...
Page 225 System Integration Unit (SIU) Table 8-29. SIU_HLTACK0 Register Field Descriptions (continued) Field Description HLTACK29 Halt acknowledge bit 29. When this bit is set, the I C_A module is halted. HLTACK31 Halt acknowledge bit 31. When this bit is set, the ADC module is halted. Offset: SIU_HLTACK1: SIU_BASE + 0x09B0 Access: User read-only...
Page 226 System Integration Unit (SIU) 8.3.2.25 eMIOS Select Register n (SIU_EMIOS_SELn) The SIU_EMIOS_SELn register specifies the source for the eMIOS[31:0] input channels, thus allowing the timer input channels to come from the pins, or from the deserialized output of one of the four DSPI modules.
Page 227 System Integration Unit (SIU) Offset: SIU_BASE + 0x09C0 Access: User read/write EMIOSSEL7 EMIOSSEL6 EMIOSSEL5 EMIOSSEL4 Reset EMIOSSEL3 EMIOSSEL2 EMIOSSEL1 EMIOSSEL0 Reset Figure 8-33. eMIOS Select Register 3 (SIU_EMIOS_SEL3) Table 8-31. SIU_EMIOS_SELn Field Descriptions Field Description EMIOSSELn eMIOS Channel[n] connection options. 0000–0011 eMIOS[n] input pin.
Page 228 System Integration Unit (SIU) Table 8-32. SIU_ISEL2A Field Descriptions Field Description ESEL15 External IRQ Input Select 15. Specifies input for IRQ15. 00 PH15 pin. 01 PJ15 pin. 10 Reserved. 11 Reserved. ESEL14 External IRQ Input Select 14. Specifies input for IRQ14. 00 PH14 pin.
Page 229 System Integration Unit (SIU) Table 8-32. SIU_ISEL2A Field Descriptions (continued) Field Description ESEL6 External IRQ Input Select 6. Specifies input for IRQ6. 00 PH6 pin. 01 PJ6 pin. 10 PK6 pin. 11 Reserved. ESEL5 External IRQ Input Select 5. Specifies input for IRQ5. 00 PH5 pin.
Page 230 System Integration Unit (SIU) 8.3.2.27 Parallel GPIO Pin Data Output Register 0 (SIU_PGPDO0) The SIU_PGPDO0 register contains the parallel GPIO pin data output for PB[0:15]. Reads and writes to this register are coherent with the registers SIU_GPDO16_19, SIU_GPDO20_23, SIU_GPDO24_27, and SIU_GPDO28_31. NOTE On the PXN20, the port A pins are general-purpose inputs only.
Page 231 System Integration Unit (SIU) 8.3.2.29 Parallel GPIO Pin Data Output Register 2 (SIU_PGPDO2) The SIU_PGPDO2 register contains the Parallel GPIO Pin Data Output for PE[0:15] and PF[0:15]. Reads and writes to this register are coherent with the registers SIU_GPDO64_67, SIU_GPDO68_71, SIU_GPDO72_75, SIU_GPDO76_79, SIU_GPDO80_83, SIU_GPDO84_87, SIU_GPDO88_91, and SIU_GPDO92_95.
Page 232 System Integration Unit (SIU) Offset: SIU_BASE + 0x0C10 Access: User read/write PJ0:PJ15 Reset PK0:PK10 Reset Figure 8-39. Parallel GPIO Pin Data Output Register 4 (SIU_PGPDO4) 8.3.2.32 Parallel GPIO Pin Data Input Register 0 (SIU_PGPDI0) Reads to the SIU_PGPDI0 register provide the parallel GPIO pin data input for PA[0:15] and PB[0:15]. Writes have no effect.
Page 233 System Integration Unit (SIU) Offset: SIU_BASE + 0x0C44 Access: User read-only PC0:PC15 Reset PD0:PD15 Reset Figure 8-41. Parallel GPIO Pin Data Input Register 1 (SIU_PGPDI1) 8.3.2.34 Parallel GPIO Pin Data Input Register 2 (SIU_PGPDI2) Reads to the SIU_PGPDI2 register provide the parallel GPIO pin data input for PE0:PE15 and PF0:PF15. Writes have no effect.
Page 234 System Integration Unit (SIU) Offset: SIU_BASE + 0x0C4C Access: User read-only PG0:PG15 Reset PH0:PH15 Reset Figure 8-43. Parallel GPIO Pin Data Input Register 3 (SIU_PGPDI3) 8.3.2.36 Parallel GPIO Pin Data Input Register 4 (SIU_PGPDI4) Reads to the SIU_PGPDI4 register provide the parallel GPIO pin data input for PJ0:PJ15 and PK0:PK10. Writes have no effect.
Page 235 System Integration Unit (SIU) Writes to this register are coherent with the registers SIU_GPDO16_19, SIU_GPDO20_23, SIU_GPDO24_27, and SIU_GPDO28_31. Offset: SIU_BASE + 0x0C84 Access: User write-only PB_MASK[0:15] Reset PB[0:15] Reset Figure 8-45. Masked Parallel GPIO Pin Data Output Register 1 (SIU_MPGPDO1) 8.3.2.38 Masked Parallel GPIO Pin Data Output Register 2 (SIU_MPGPDO2) The SIU_MPGPDO2 register contains the masked parallel GPIO pin data output for PC[0:15].
Page 236 System Integration Unit (SIU) Offset: SIU_BASE + 0x0C8C Access: User write-only PD_MASK[0:15] Reset PD[0:15] Reset Figure 8-47. Masked Parallel GPIO Pin Data Output Register 3 (SIU_MPGPDO3) 8.3.2.40 Masked Parallel GPIO Pin Data Output Register 4 (SIU_MPGPDO4) The SIU_MPGPDO4 register contains the masked parallel GPIO pin data output for PE[0:15]. Writes to this register are coherent with registers SIU_GPDO64_67, SIU_GPDO68_71, SIU_GPDO72_75, and SIU_GPDO76_79.
Page 237 System Integration Unit (SIU) Offset: SIU_BASE + 0x0C94 Access: User write-only PF_MASK[0:15] Reset PF[0:15] Reset Figure 8-49. Masked Parallel GPIO Pin Data Output Register 5 (SIU_MPGPDO5) 8.3.2.42 Masked Parallel GPIO Pin Data Output Register 6 (SIU_MPGPDO6) The SIU_MPGPDO6 register contains the masked parallel GPIO pin data output for PG[0:15] Writes to this register are coherent with registers SIU_GPDO96_99, SIU_GPDO100_103, SIU_GPDO104_107, and SIU_GPDO108_111.
Page 238 System Integration Unit (SIU) Offset: SIU_BASE + 0xC9C Access: User write-only PH_MASK[0:15] Reset PH[0:15] Reset Figure 8-51. Masked Parallel GPIO Pin Data Output Register 7 (SIU_MPGPDO7) 8.3.2.44 Masked Parallel GPIO Pin Data Output Register 8 (SIU_MPGPDO8) The SIU_MPGPDO8 register contains the masked parallel GPIO pin data output for PJ[0:15]. Writes to this register are coherent with registers SIU_GPDO128_131, SIU_GPDO132_135, SIU_GPDO136_139, and SIU_GPDO140_143.
Page 239 System Integration Unit (SIU) Offset: SIU_BASE + 0x0CA4 Access: User write-only PK_MASK[0:10] Reset PK[0:10] Reset Figure 8-53. Masked Parallel GPIO Pin Data Output Register 9 (SIU_MPGPDO9) 8.3.2.46 Masked Serial GPO Register for DSPI_A High (SIU_DSPIAH) The SIU_DSPIAH register allows any combination of bits in the top half of the 32-bit serialized data frame from DSPI_A to be updated with a single 32-bit write operation, while allowing other bits to maintain their previous state.
Page 240 System Integration Unit (SIU) 8.3.2.47 Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL) The SIU_DSPIAL register allows any combination of bits in the bottom half of the 32-bit serialized data frame from DSPI_A to be updated with a single 32-bit write operation, while allowing other bits to maintain their previous state.
Page 241 System Integration Unit (SIU) Offset: SIU_BASE + 0x0D08 Access: User read/write R MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK Reset R DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA...
Page 242 System Integration Unit (SIU) Table 8-36. SIU_DSPIBL Field Descriptions Field Description MASKn Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_B. 0 The previous value defined by GPO for DSPI_B is maintained. 1 The corresponding GPO for DSPI_B is written with the value defined by the DATAn field. DATAn Pin Data Out.
Page 243 System Integration Unit (SIU) maintain their previous state. This is accomplished by writing a 16-bit masked value coherently with an update value contained in a 16-bit output field, and only updating those bits in the output register for which the corresponding mask bit is set. Offset: SIU_BASE + 0x0D14 Access: User read/write...
Page 244 System Integration Unit (SIU) Table 8-39. SIU_DSPIDH Field Descriptions Field Description MASKn Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_D. 0 The previous value defined by GPO for DSPI_D is maintained. 1 The corresponding GPO for DSPI_D is written with the value defined by the DATAn field. DATAn Pin Data Out.
Page 245 System Integration Unit (SIU) Offset: SIU_BASE + 0x0D44 Access: User read/write EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS Reset EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS...
Page 246 System Integration Unit (SIU) 8.3.2.56 eMIOS Select Register for DSPI_B (SIU_EMIOSB) The SIU_EMIOSB register selects the output serialized source for the DSPI_B channel. Offset: SIU_BASE + 0x0D54 Access: User read/write EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS...
Page 247 System Integration Unit (SIU) Table 8-44. SIU_DSPIBHLB Field Descriptions Field Description DSPIBHn Data Path Enable for DSPI_B High. 0 Data path disabled to DSPI_B High. 1 Data path enabled to DSPI_B High. DSPIBLn Data Path Enable for DSPI_B Low. 0 Data path disabled to DSPI_B Low. 1 Data path enabled to DSPI_B Low.
Page 248 System Integration Unit (SIU) Offset: SIU_BASE + 0x0D68 Access: User read/write DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI Reset DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI DSPI...
Page 249 System Integration Unit (SIU) 8.3.2.61 SIU_DSPIDH/L Select Register for DSPI_D (SIU_DSPIDHLD) The SIU_DSPIDHLD register enables the data path from the Masked Serial GPO register for DSPI_D to the equivalent bit position in the DSPI_D channel frame. Offset: SIU_BASE + 0x0D78 Access: User read/write DSPI DSPI...
Page 250 System Integration Unit (SIU) Functional Description The following sections provide an overview of the SIU operation. 8.4.1 System Configuration 8.4.1.1 Boot Configuration During the assertion of RESET, the BOOTCFG pin is used to load a value into the SIU_RSR[BOOTCFG] bit, so the BAM program can determine the location of the reset configuration half word (RCHW), the boot mode to be initiated, and whether to initiate a CAN or SCI boot.
Page 251 System Integration Unit (SIU) combined overrun interrupt request is used in the device, and the individual overrun requests are not connected. Each IRQ pin has a programmable filter for rejecting glitches on the IRQ signals. The filter length for the IRQ pins is specified in the external IRQ digital filter register (SIU_IDFR).
Page 252 System Integration Unit (SIU) an ADC external trigger input. As shown in the figure, the start of conversion input of the ADC can be connected to the PE10 pin, the PE11 pin, PE12 pin, PE13 pin, or the PIT2 channel. The external injected trigger are multiplexed in the same manner.
Page 253 System Integration Unit (SIU) IRQ[0] SIU_ISEL1[30:31] SIU_ISEL2[30:31] SIU_ISEL2A[30:31] Figure 8-72. SIU External Interrupt Input Multiplexing 8.4.5.3 SIU EMIOS/DSPI Multiplexing The Serialization Data Register from each of the four DSPI modules can be connected to the EMIOS channel outputs (if selected by the SIU_EMIOSx registers) or the Masked Serial GPO registers (if selected by the SIU_DSPIxHLx registers, as shown in Figure 8-73.
Page 254 System Integration Unit (SIU) SIU_EMIOSA DSPIA EMIOS channel output DSPI Serialization Data Register SIU_DSPIAHLA SIU_DSPIA SIU_EMIOSB DSPIB EMIOS channel output DSPI Serialization Data Register SIU_DSPIAHLB SIU_DSPIB SIU_EMIOSC DSPIC EMIOS channel output DSPI Serialization Data Register SIU_DSPIAHLC SIU_DSPIC SIU_EMIOSD DSPID EMIOS channel output DSPI Serialization Data Register SIU_DSPIAHLD SIU_DSPID...
Page 255 Chapter 9 Boot Assist Module (BAM) Introduction The PXN20 boot assist module (BAM) is a 4 KB block of read-only memory (ROM) that is programmed by Freescale using variable length encoding (VLE) code. The BAM program is executed by the e200z6 when the PXN20 performs a power-on-reset (POR) or any other reset for which the CRP_Z6VEC register remains in its reset state.
Page 256 Boot Assist Module (BAM) 9.1.2 Modes of Operation The BAM has the following modes of operation: • Normal mode • Debug mode • Internal-boot mode • Serial-boot mode 9.1.2.1 Normal Mode In normal operation the BAM responds to all read requests within its address space. The e200z6 core executes the BAM program after the negation of RESET if the CRP_Z6VEC register value is 0xFFFF_FFFC.
Page 257 Boot Assist Module (BAM) 9.2.2 Register Descriptions The BAM module does not have any registers. Functional Description 9.3.1 BAM Program Resources The BAM program uses/initializes these MCU resources: • The BOOTCFG field in the reset status register (SIU_RSR) determines the boot option •...
Page 258 Boot Assist Module (BAM) Table 9-2. Boot Modes (continued) Censorship Serial Boot Internal Serial Boot Mode Name BOOTCFG Control Control Flash Nexus State Password 0x00FF_FDE0 0x00FF_FDE2 State Serial—Flash Password Don't care 0x55AA Enabled Disabled Flash Serial—Public Password Any other value Disabled Enabled Public...
Page 259 Boot Assist Module (BAM) Serial-boot flash password at 0x00FF_FDD8 – 0x00FF_FDDF: Serial boot password (0x00FF_FDD8)–0xFEED (factory default) Serial boot password (0x00FF_FDDA)–0xFACE (factory default) Serial boot password (0x00FF_FDDC)–0xCAFE (factory default) Serial boot password (0x00FF_FDDE)– 0xBEEF (factory default) Figure 9-2. Serial Boot Flash Password If the BAM fails to find a valid RCHW in internal-boot mode then serial-boot mode is entered.
Page 260 Boot Assist Module (BAM) Table 9-3. MMU Configuration for an Internal Boot Logical Base Physical Base Entr Region Size Attributes Address Address reserved 0x2000_0000 0x2000_0000 256 MB Cache enabled Not guarded Big Endian Global PID SRAM 0x4000_0000 0x4000_0000 256 KB Cache inhibited Not guarded Big Endian...
Page 261 Boot Assist Module (BAM) Figure 9-3 shows the fields of the RCHW. Offset: BOOT_BLOCK_ADDRESS + 0x0000 Access: User read-only BOOT ID Reset Reset Figure 9-3. RCHW Fields Table 9-5. Internal Boot RCHW Field Descriptions Field Description Watchdog timer enable. This bit determines if the software watchdog timer is disabled. 0 Disable software watchdog timer 1 Software watchdog timer maintains its default state out of reset, (i.e.,enabled).
Page 262 Boot Assist Module (BAM) Offset: BOOT_BLOCK_ADDRESS + 0x0004 Access: User read-only Reset Reset Figure 9-4. Reset Boot Vector 9.3.3.2 Serial-Boot Mode Features In this mode of operation, the BAM code configures FlexCAN_A and eSCI_A for serial download of a user program. Unused message buffers in FlexCAN_A are used for stack and global variables. The system clock is selected directly from main crystal oscillator output;...
Page 263 Boot Assist Module (BAM) NRZ signal SYNC_SEG Time segment 1 Time segment 2 Time quanta Time quanta Time quanta 1 bit time Sample point Transmit point 1 time quanta = 4 system clock periods Figure 9-5. FlexCAN Bit Timing The eSCI is configured for one start bit, eight data bits, no parity, and one stop bit. It operates at a baud rate = system clock / 832.
Page 264 Boot Assist Module (BAM) In CAN serial-boot mode, the eSCI_A RXD_A pad reverts to GPIO input. The ensuing download protocol is assumed to be all through the CAN, eSCI is disabled. If the eSCI byte is received first, the CAN_A controller is disabled and its pad reprogrammed to the GPIO, the TXD_A signal is reconfigured as an output.
Page 265 Boot Assist Module (BAM) 9.3.3.2.3 Serial-Boot Mode Processing The BAM program executes the serial boot as following: 1. Download 64-bit password. The received 8-byte password is checked for validity. It is checked to ensure that none of the 4  16-bit halfwords are illegal passwords, such as 0x0000 or 0xFFFF. A password must have at least one 0 and one 1 in each halfword lane to be considered legal.
Page 266 Boot Assist Module (BAM) NOTE In the PXN20, the SRAM is protected by 64-bit wide error correction code (ECC). In the general case, this means any write to uninitialized SRAM must be 64 bits wide, otherwise an ECC error may occur. Therefore the BAM buffers downloaded data until 8 bytes have been received, and then does a single 64-bit wide write.
Page 267 Boot Assist Module (BAM) Table 9-10. eSCI Serial-Boot Mode Download Protocol Protocol BAM Response Host Sent Message Action Step Message 64-bit password MSB first 64-bit password Password checked for validity and compared against stored password. Platform Watchdog timer is refreshed if the password check is successful.
Page 268 Boot Assist Module (BAM) PXN20 Microcontroller Reference Manual, Rev. 1 9-14 Freescale Semiconductor...
Page 269 Chapter 10 Interrupts and Interrupt Controller (INTC) 10.1 Introduction This chapter describes the interrupts and the interrupt controller (INTC), which schedules interrupt requests (IRQs) from software and internal peripherals to the e200z6 and e200z0 cores. The INTC provides interrupt prioritization and preemption, interrupt masking, interrupt priority elevation, and protocol support.
Page 270 Interrupts and Interrupt Controller (INTC) Interrupt Processor 1 Pop Acknowledge Processor 1 Push/Update/Acknowledge from Processor 1 Interrupt Pushed Request to Priority Priority Processor 1 Processor 1 Processor 1 Popped Current NOTE: Processor 0 is Z6 Current Priority Priority Priority Priority and Processor 1 is Z0.
Page 271 Interrupts and Interrupt Controller (INTC) 10.1.2 Interrupt Controller Features • Supports 308 peripheral and eight software-settable interrupt request sources. • Each interrupt source can be steered by software to processor 0 (Z6), processor 1 (Z0), or both processors interrupt request outputs. NOTE By default, processor 0 (Z6) receives all interrupt requests, so backward compatibility with single processor systems is maintained.
Page 272 Interrupts and Interrupt Controller (INTC) External interrupt e200z6 Interrupt IRQs exception request controller e200z0 (INTC) core Figure 10-2. INTC Software Vector Mode Typical program flow for software vector mode is shown in Figure 10-3. Address Instructions Address Instructions ISR 0 address ISR 0 VTBA Prolog...
Page 273 Interrupts and Interrupt Controller (INTC) IVPR 19 20 Vector base 0x000 IVOR4 0x0000_0040 Software Vector Mode Interrupt Exception Handler Address 19 20 Vector base 0x040 Figure 10-4. Z0 Software Vector Mode: Interrupt Exception Handler Address Calculation IVPR PREFIX 0x0000 + IVOR4 0x0000 OFFSET 0x00...
Page 274 Interrupts and Interrupt Controller (INTC) the size of a write does not affect the operation of the write. Those values and sizes written to this register neither update the INTC_EOIR_PRCn contents nor affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0s to the INTC_EOIR_PRCn.
Page 275 Interrupts and Interrupt Controller (INTC) IVPR 19 20 Vector base 0x000 Hardware Vector Mode Offset 0x0_0000 Vector 0b00 Hardware Vector Mode Interrupt Exception Handler Address Vector base Vector 0b00 Figure 10-7. Z0 Hardware Vector Mode: Interrupt Exception Handler Address Calculation IVPR PREFIX 0x0000...
Page 276 Interrupts and Interrupt Controller (INTC) 10.3 Memory Map and Registers 10.3.1 INTC Memory Map Table 10-1 shows the INTC memory map. Table 10-1. INTC Memory Map Offset from Reset INTC_BASE_ADDR Register Access Section/Page Value (0xFFF4_8000) 0x0000 INTC_MCR—INTC module configuration register 0x0000_0000 10.3.2.1/10-9 0x0004...
Page 277 Interrupts and Interrupt Controller (INTC) • In hardware vector mode, guarded writes to the INTC_CPR or INTC_EOIR complete before the interrupt acknowledge signal from the processor asserts. 10.3.2 Register Descriptions With the exception of the INTC_SSCIn and INTC_PSRn registers, all registers are 32 bits in width. Any combination of accessing the four bytes of a register with a single access is supported, provided that the access does not cross a register boundary.
Page 278 Interrupts and Interrupt Controller (INTC) Table 10-2. INTC_MCR Field Descriptions (continued) Field Description VTES_PRC0 For software mode only, the Vector Table Entry Size for Processor 0 (Z6). The VTES_PRC0 bit controls the number of 0s to the right of INTVEC_PRC0 in INTC_IACKR_PRC0. If the contents of INTC_IACKR_PRC0 are used as an address of an entry in a vector table, then the number of rightmost 0s will determine the size of each vector table entry.
Page 279 Interrupts and Interrupt Controller (INTC) NOTE A store to raise the PRI field which closely precedes an access to a shared resource can result in a non-coherent access to that resource unless an mbar or msync followed by an isync sequence of instructions is executed between the accesses.
Page 280 Interrupts and Interrupt Controller (INTC) 10.3.2.3 INTC Current Priority Register for Processor 1 (Z0) (INTC_CPR_PRC1) Offset: INTC_BASE_ADDR + 0x000C Access: User read/write Reset Reset Figure 10-11. INTC Current Priority Register for Processor 1 (Z0) (INTC_CPR_PRC1) Table 10-5. INTC_CPR_PRC1 Field Descriptions Field Description Priority.
Page 281 Interrupts and Interrupt Controller (INTC) Table 10-6. INTC_IACKR_PRC0 Field Descriptions Field Description VTBA_PRC0 Vector Table Base Address for Processor 0 (Z6). VTBA_PRC0 can be the base address of a vector table of addresses of ISRs for processor 0 (Z6). The VTBA_PRC0 only uses the leftmost 20 bits when the VTES_PRC0 bit in INTC_MCR is asserted.
Page 282 Interrupts and Interrupt Controller (INTC) 10.3.2.5 INTC Interrupt Acknowledge Register for Processor 1 (Z0) (INTC_IACKR_PRC1) Offset: INTC_BASE_ADDR + 0x0014 Access: User read/write VTBA_PRC1 (most significant 16 bits) Reset INTVEC_PRC1 VTBA_PRC1 (5 least-significant bits) Reset When the VTES_PRC1 bit in INTC_MCR is asserted, INTVEC_PRC1 is shifted to the left one bit. Bit 29 is read as 0.
Page 283 Interrupts and Interrupt Controller (INTC) 10.3.2.7 INTC End-of-Interrupt Register for Processor 1 (Z0) (INTC_EOIR_PRC1) Offset: INTC_BASE_ADDR + 0x001C Access: User write-only INTC_EOIR_PRC1 Reset INTC_EOIR_PRC1 Reset Figure 10-15. INTC End-of-Interrupt Register for Processor 1 (Z0) (INTC_EOIR_PRC1) The register’s function is the same as for processor 0 (Z6) as described in Section 10.3.2.6, INTC End-of-Interrupt Register for Processor 0 (Z6) (INTC_EOIR_PRC0).
Page 284 Interrupts and Interrupt Controller (INTC) Table 10-8. INTC_SSCIR[0:7] Field Descriptions Field Description Set Flag Bits. Writing a 1 sets the corresponding CLRn bit. Writing a 0 has no effect. Each SETn is always read as a 0. Clear Flag Bits. CLRn is the flag bit. Writing a 1 to CLRnx clears it provided that a 1 is not written simultaneously to its corresponding SETn bit.
Page 285 Interrupts and Interrupt Controller (INTC) Table 10-9. INTC_PSR0_3–INTC_PSR312_315 Field Descriptions Field Description PRC_SEL0– Processor Select. If an interrupt source is enabled, PRC_SELn selects whether the interrupt request is to PRC_SEL315 be sent to processor 0 (Z6), processor 1 (Z0), or both. See Table 10-11.
Page 286 Interrupts and Interrupt Controller (INTC) Table 10-10. INTC Priority Select Register Address Offsets INTC_PSRn_n Offset Address INTC_PSRn_n Offset Address INTC_PSR108_111 0x00AC INTC_PSR268_271 0x014C INTC_PSR112_115 0x00B0 INTC_PSR272_275 0x0150 INTC_PSR116_119 0x00B4 INTC_PSR276_279 0x0154 INTC_PSR120_123 0x00B8 INTC_PSR280_283 0x0158 INTC_PSR124_127 0x00BC INTC_PSR284_287 0x015C INTC_PSR128_131 0x00C0 INTC_PSR288_291 0x0160...
Page 287 Interrupts and Interrupt Controller (INTC) 10.4 Functional Description 10.4.1 External Interrupt Request Sources The INTC has two types of interrupt requests, peripheral and software settable. The assignments between the interrupt requests from the modules to the vectors for input to the CPU are shown in Table 10-12.
Page 288 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x00A0 0x0828 eDMA–Error 1 eDMA 0x00B0 0x082C eDMA–0 0x00C0 0x0830 eDMA–1 0x00D0 0x0834 eDMA–2 0x00E0...
Page 289 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x0160 0x0858 eDMA–11 eDMA (continued) 0x0170 0x085C eDMA–12 0x0180 0x0860 eDMA–13 0x0190 0x0864 eDMA–14 0x01A0...
Page 290 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x0300 0x08C0 (see Interrupt vectors 314–315) 0x0310 0x08C4 0x0320 0x08C8 PLL Loss Of Clock 0x0330 0x08CC PLL Loss Of Lock...
Page 291 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x04A0 0x0928 EMIOS 16 EMIOS channels 0 to 23 (see Interrupt vectors 0x04B0 0x092C EMIOS 17...
Page 292 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x0650 0x0994 MLB Channel Interrupt 4 MLB_DIM (continued) 0x0660 0x0998 MLB Channel Interrupt 5 0x0670 0x099C MLB Channel Interrupt 6...
Page 293 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x07F0 0x09FC FLEXCAN_A Bus Off and Warning FlexCAN_A 0x0800 0x0A00 FLEXCAN_A Error 0x0810 0x0A04 Reserved for FLEXCAN_A Wake...
Page 294 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x09A0 0x0A68 PIT6 (continued) 0x09B0 0x0A6C PIT7 0x09C0 0x0A70 PIT8 0x09D0 0x0A74 FLEXCAN_B Bus Off and Warning FlexCAN_B 0x09E0...
Page 295 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x0B20 0x0AC8 FLEXCAN_C Bus Off and Warning FlexCAN_C 0x0B30 0x0ACC FLEXCAN_C Error 0x0B40 0x0AD0 Reserved for FLEXCAN_C Wake...
Page 296 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x0C70 0x0B1C FLEXCAN_D Bus Off and Warning FlexCAN_D 0x0C80 0x0B20 FLEXCAN_D Error 0x0C90 0x0B24 Reserved for FLEXCAN_D Wake...
Page 297 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x0DC0 0x0B70 FLEXCAN_E Bus Off and Warning FlexCAN_E 0x0DD0 0x0B74 FLEXCAN_E Error 0x0DE0 0x0B78 Reserved for FLEXCAN_E Wake...
Page 298 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x0F10 0x0BC4 FLEXCAN_F Bus Off and Warning FlexCAN_F 0x0F20 0x0BC8 FLEXCAN_F Error 0x0F30 0x0BCC Reserved for FLEXCAN_F Wake...
Page 299 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x1060 0x0C18 EMIOS_24 EMIOS channels 24 to 31 (see Interrupt vectors 0x1070 0x0C1C EMIOS_25 58–81)
Page 300 Interrupts and Interrupt Controller (INTC) Table 10-12. PXN20 External Interrupt Requests (continued) Vector e200z6 Hardware e200z0 Hardware PXN20 Vector Vector Type Number Vector Mode Offset Vector Mode Offset 0x1210 0x0C84 FlexRay_FANE_F FlexRay (continued) 0x1220 0x0C88 FlexRay_RBIF 0x1230 0x0C8C FlexRay_TBIF 0x1240 0x0C90 Reserved Soft MediaLB...
Page 301 Interrupts and Interrupt Controller (INTC) NOTE The peripheral or software settable interrupt request asserts when the PRIn value in the interrupt priority select register (INTC_PSRn) is greater than the PRIn value in interrupt current priority register (INTC_CPR). If an asserted peripheral or software settable interrupt request negates before the processor acknowledges its request, the interrupt request can reassert and remain asserted.
Page 302 Interrupts and Interrupt Controller (INTC) The time from the write to the SETn bit to the time that the INTC starts to drive the interrupt request to the processor is four clocks. 10.4.1.3 Unique Vector for Each Interrupt Request Source Each peripheral and software settable interrupt request is assigned a hardwired unique 9-bit vector.
Page 303 Interrupts and Interrupt Controller (INTC) 10.4.2.1.4 Priority Comparator Submodule The priority comparator submodule compares the highest priority output from the associated priority arbitrator submodule with PRI in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1. If the priority comparator submodule detects that the highest priority is higher than the current priority, then it asserts the interrupt request to the associated processor.
Page 304 Interrupts and Interrupt Controller (INTC) 10.4.3 Details on Handshaking with Processor 10.4.3.1 Software Vector Mode Handshaking 10.4.3.1.1 Acknowledging Interrupt Request to Processor A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along with the handshake near the end of the interrupt exception handler, is shown in Figure 10-20.
Page 305 Interrupts and Interrupt Controller (INTC) Clock Interrupt Request to Processor Hardware Vector Enable Interrupt Vector Interrupt Acknowledge Read INTC_IACKR_PCRn Write INTC_EOIR_PCRn INTVEC in INTC_IACKR_PCRn PRI in INTC_CPR_PCRn Peripheral Interrupt Request 100 Figure 10-20. Software Vector Mode Handshaking Timing Diagram 10.4.3.2 Hardware Vector Mode Handshaking A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode and handshaking near the end of the interrupt exception handler is shown in...
Page 306 Interrupts and Interrupt Controller (INTC) Clock Interrupt Request to Processor Hardware Vector Enable Interrupt Vector Interrupt Acknowledge Read INTC_IACKR_PCRn Write INTC_EOIR_PCRn INTVEC in INTC_IACKR_PCRn PRI in INTC_CPR_PCRn Peripheral Interrupt Request 100 Figure 10-21. Hardware Vector Mode Handshaking Timing Diagram 10.5 Initialization/Application Information 10.5.1 Initialization Flow...
Page 307 Interrupts and Interrupt Controller (INTC) 10.5.2.1 Software Vector Mode interrupt_exception_handler: code to create stack frame, save working register, and save SRR0 and SRR1 r3,INTC_IACKR_PRCn@ha # form adjusted upper half of INTC_IACKR_PRCn address r3,INTC_IACKR_PRCn@l(r3) # load INTC_IACKR_PRCn, which clears request to processor r3,0x0(r3) # load address of ISR from vector table wrteei...
Page 308 Interrupts and Interrupt Controller (INTC) code to create stack frame, save working register, and save SRR0 and SRR1 wrteei # enable processor recognition of interrupts code to save rest of context required by e500 EABI ISRx # branch to ISR for interrupt with vector x epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor...
Page 309 Interrupts and Interrupt Controller (INTC) 10.5.4 Order of Execution An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors associated with each of their peripheral or software settable interrupt requests. However, if multiple peripheral or software settable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted.
Page 310 Interrupts and Interrupt Controller (INTC) 10.5.5 Priority Ceiling Protocol 10.5.5.1 Elevating Priority The PRI field in INTC current priority register (INTC_CPR_PRC0 or INTC_CPR_PRC1) is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs that share a resource. This protocol allows coherent accesses of the ISRs to that shared resource.
Page 311 Interrupts and Interrupt Controller (INTC) timing diagram for this scenario, and Table 10-14 explains the events. The example is for software vector mode, but except for the method of retrieving the vector and acknowledging the interrupt request to the processor, hardware vector mode is identical. Clock Interrupt Request to Processor...
Page 312 Interrupts and Interrupt Controller (INTC) Event Description Interrupt exception handler epilog writes to INTC_EOIR. LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop from LIFO is the priority from before peripheral interrupt request 100 interrupted. ISR108 now can access data block coherently after interrupt exception handler executes rfi instruction.
Page 313 Interrupts and Interrupt Controller (INTC) of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher priority portion, to set a SETn bit in INTC software set/clear interrupt registers (INTC_SSCIR0–INTC_SSCIR7). Writing a 1 to SETn causes a software settable interrupt request. This software settable interrupt request usually has a lower PRIn value in the INTC_PSRn, and therefore does not cause preemptive scheduling inefficiencies.
Page 314 Interrupts and Interrupt Controller (INTC) 10.5.9 Negating an Interrupt Request Outside of its ISR 10.5.9.1 Negating an Interrupt Request as a Side Effect of an ISR Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt request.
Page 315 Interrupts and Interrupt Controller (INTC) load INTC_IACKR_PRCn if stacked PRI values are not depleted, branch to push_lifo NOTE Reading the INTC_IACKR_PRCn acknowledges the interrupt request to the processor and updates the INTC_CPR_PRCn[PRI] with the priority of the preempting interrupt request. If the processor recognition of interrupts is disabled during the LIFO restoration, interrupt requests to the processor can go undetected.
Page 316 Interrupts and Interrupt Controller (INTC) request DIRS0 eDMA DIRS1 SIU_EISR SIU_DIRSR EIF0 DIRS0 EIF1 DIRS1 External DIRS0 EIF2 IRQ pins or DIRS1 IMUX EIF3 internal EIF4 Interrupt sources • • • • controller • • • • EIF15 EIF4–EIF15 NMI1 NMI0 SIU_OSR Secondary...
Page 317 Interrupts and Interrupt Controller (INTC) Great care must be taken when using the priority elevation as it can enable a master to starve the rest of the masters in the system. For more information, see Chapter 19, Error Correction Status Module (ECSM). 10.7.3 eDMA Dynamic Interrupt Priority Elevation The eDMA can handle dynamic priority elevation via the Bandwidth Control (BWC) field of the transfer...
Page 318 Interrupts and Interrupt Controller (INTC) PXN20 Microcontroller Reference Manual, Rev. 1 10-50 Freescale Semiconductor...
Page 319 Chapter 11 General-Purpose Static RAM (SRAM) 11.1 Introduction This chapter describes the general-purpose static RAM (SRAM) for the PXN20 family. The PXN20 provides 592 KB of SRAM. The PXN21 provides 128 KB of SRAM. 11.1.1 Block Diagram AHB Crossbar Switch 4 x 128 4 x 128 SRAM...
Page 320 General-Purpose Static RAM (SRAM) AHB Crossbar Switch Memory Protection Unit 4 x 128 4 x 128 Page Buffer Page Buffer PFlash Controller SRAM SRAM Peripheral Peripheral Controller Controller Bridge A Bridge B 2 MB Flash (with small blocks) (ECC) 128 KB SRAM (with ECC) Figure 11-2.
Page 321 General-Purpose Static RAM (SRAM) 11.1.3 Modes of Operation There are two main operating modes of DSPI: normal mode and sleep mode. These modes are briefly described in this section. 11.1.3.1 Normal (Functional) Mode Normal mode allows for reads and writes of the SRAM memory arrays. 11.1.3.2 Sleep Mode The size of RAM retained during Sleep mode is controlled in the CRP, in CRP_PSCR[RAMSEL[2:0]].
Page 322 General-Purpose Static RAM (SRAM) The intent of this is to detect all odd-bit failures, all two-bit failures, some three-bit failures, and some multi-bit failures, with regard to IEC 61508-7 A.5.6. NOTE The SRAM does not detect all errors greater than 2 bits. Internal SRAM write operations are performed on the following byte boundaries: •...
Page 323 General-Purpose Static RAM (SRAM) Table 11-1. Number of Wait States Required for SRAM Operations Current Operation Previous Operation Number of Wait States Required Idle Pipelined read Burst read 64-bit write Read (read from the same address) 8-, 16-, or 32-bit write (read from a different address) Pipelined read Read...
Page 324 General-Purpose Static RAM (SRAM) • Power-on reset • Low-voltage inhibit (LVI) reset • External reset • PLL loss of clock (if enabled) • PLL loss of lock (if enabled) The user code must re-initialize the RAM after any of the above resets; otherwise, an ECC event might occur.
Page 325 General-Purpose Static RAM (SRAM) addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128? bdnz init_ram_loop # loop for 80k of SRAM PXN20 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 11-7...
Page 326 General-Purpose Static RAM (SRAM) PXN20 Microcontroller Reference Manual, Rev. 1 11-8 Freescale Semiconductor...
Page 327 Chapter 12 Flash Memory Array and Control 12.1 Introduction This section presents information about the following components on this device: • The flash memory block • The platform flash memory controller The primary function of the flash memory module is to serve as electrically programmable and erasable non-volatile memory.
Page 328 Flash Memory Array and Control Flash array blocks Low-address space—256 KB Low-address space 8 x 16 KB + 2 x 64 KB Mid-address space—256 KB 2 x 128 KB Mid-address space High-address space—1.5 MB 2 x 256 KB High-address space 2 x 256 KB 2 x 256 KB Figure 12-1.
Page 329 Flash Memory Array and Control 12.1.2 Features The flash memory module has these major features: • Support for a 64-bit data bus for instruction fetch. • Support for a 32-bit data bus for CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported.
Page 330 Flash Memory Array and Control 12.1.3.3 User Test Mode (UTest) User test mode (UTest) provides a limited set of tests to end users. 12.2 External Signal Description is the only externally visible power supply that is necessary for programming and erasing the flash array.
Page 331 Flash Memory Array and Control Table 12-1. Flash Memory Map (continued) Offset from FLASH_BASE Block Partition (0x0000_0000) 0x0008_0000 High-address space 0x000C_0000 0x0010_0000 0x0014_0000 0x0018_0000 0x001C_0000 0x0020_0000–0x00FF_BFFF Reserved 0x00FF_C000–0x00FF_FDD7 General use 0x00FF_FDD8 Serial passcode (0xFEED_FACE_CAFE_BEEF) 0x00FF_FDE0 Censorship control word (0x55AA_55AA) 0x00FF_FDE4 General use 0x00FF_FDE8 LML reset configuration (0x0010_0000)
Page 332 Flash Memory Array and Control Table 12-2. Flash Configuration Register Memory Map (continued) Offset from FLASH_REGS_BASE Register Access Reset Value Section/Page (0xFFFF_8000) 0x0028 PFSACC—Platform flash supervisor access control 0x00FF_FE08 12.3.2.10/12-21 register 0x002C PFDACC—Platform flash data access control register 0x00FF_FE10 12.3.2.11/12-23 0x0030 –...
Page 333 Flash Memory Array and Control Table 12-3. MCR Field Descriptions Field Description SIZE Array Space Size. The value of the SIZE field depends on the size of the flash module. For PXN20, this bit field is 0b101, indicating a 2.0 MB array size (with 1.5 MB in high-address space). SIZE is read only. Low Address Space.
Page 334 Flash Memory Array and Control Table 12-3. MCR Field Descriptions (continued) Field Description Program/Erase Good. The PEG bit indicates the completion status of the last flash program or erase sequence for which high voltage operations were initiated. The value of PEG is updated automatically during the program and erase high voltage operations.
Page 335 Flash Memory Array and Control Table 12-3. MCR Field Descriptions (continued) Field Description ESUS Erase Suspend. ESUS is used to indicate that the flash module is in erase suspend or in the process of entering a suspend state. The module is in erase suspend when ESUS = 1 and DONE = 1. ESUS can be set high only when ERS and EHV are high and PGM is low.
Page 336 Flash Memory Array and Control Because the MCR[DONE] flag can be set too soon, a delay needs to be inserted between setting the MCR[ESUS] or MCR[PSUS] and reading the same flash partition. The minimum duration of the delay should be 40 us to guarantee correct operation.
Page 337 Flash Memory Array and Control Offset: FLASH_REGS_BASE + 0x0004 Access: User read/write R LME SLOCK MLOCK Reset LLOCK Reset Figure 12-4. Low/Mid Address Block Locking Register (LML) Table 12-5. LML Field Descriptions Field Description Low/Mid Address Lock Enable. This bit is used to enable the Lock registers (SLOCK, MLOCK and LLOCK) to be set or cleared by register writes.
Page 338 Flash Memory Array and Control Table 12-5. LML Field Descriptions (continued) Field Description MLOCK[1:0] Mid Address Space Block Lock. A value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. A value of 0 in the lock register signifies that the corresponding block is available to receive program and erase pulses.
Page 339 Flash Memory Array and Control Offset: FLASH_REGS_BASE + 0x0008 Access: User read/write R HBE Reset HLOCK Reset Figure 12-5. High Address Space Block Locking Register (HBL) Table 12-6. HBL Field Descriptions Field Description High Address Lock Enable This bit is used to enable the Lock registers (HLOCK) to be set or cleared by register writes.
Page 340 Flash Memory Array and Control Offset: FLASH_REGS_BASE + 0x000C Access: User read/write R SLE LOCK LOCK Reset SLLOCK Reset Figure 12-6. Secondary Low/Mid Address Block Locking Register (SLL) Table 12-7. SLL Field Descriptions Field Description Secondary Low/Mid Address Lock Enable. This bit is used to enable the Lock registers (SSLOCK, SMLOCK, and SLLOCK) to be set or cleared by register writes.
Page 341 Flash Memory Array and Control Offset: FLASH_REGS_BASE + 0x0010 Access: User read/write MSEL Reset LSEL Reset Figure 12-7. Low/Mid Address Space Block Select Register (LMS) Table 12-8. LMS Field Descriptions Field Description MSEL[1:0] Mid Address Space Block Select. A value of 1 in the select register signifies that the block is selected for erase.
Page 342 Flash Memory Array and Control Offset: FLASH_REGS_BASE + 0x0014 Access: User read/write Reset HSEL Reset Figure 12-8. High Address Space Block Select Register (HBS) Table 12-9. HBS Field Descriptions Field Description HSEL[5:0] High Address Space Block Select. High Address Block Select has the same characteristics as LSEL. 12.3.2.7 Address Register (ADR) The Address register (ADR) provides the first failing address in the event module failures (ECC or...
Page 343 Flash Memory Array and Control Table 12-10. ADR Field Descriptions Field Description Shadow Address. The SAD bit qualifies the address captured during an ECC Event Error, Single Bit Correction, or State Machine operation. The SAD register is not writable. 0 Address Captured is from Main Array Space. 1 Address Captured is from Shadow Array Space.
Page 344 Flash Memory Array and Control Table 12-11. PFCRP0 and PFCRP1 Field Descriptions Field Description LBCFG[3:0] Line Buffer Configuration. Controls the configuration of the four line buffers in the PFLASH controller. The buffers can be organized as a pool of available resources or with a fixed partition between instruction and data buffers. In all cases, when a buffer miss occurs, it is allocated to the least recently used buffer within the group and the just-fetched entry then marked as most recently used.
Page 345 Flash Memory Array and Control Table 12-11. PFCRP0 and PFCRP1 Field Descriptions (continued) Field Description APC[2:0] Address Pipelining Control. Used to control the number of cycles between pipelined access requests. This field must be set to a value corresponding to the operating frequency of the PFLASH. The settings are documented in the PXN20 Microcontroller Data Sheet.
Page 346 Flash Memory Array and Control Table 12-11. PFCRP0 and PFCRP1 Field Descriptions (continued) Field Description PFLIM[1:0] PFLASH Prefetch Limit. Controls the prefetch algorithm used by the PFLASH prefetch controller. This field defines a limit on the maximum number of sequential prefetches that are attempted between buffer misses. In all situations when enabled, only a single prefetch is initiated on each buffer miss or hit.
Page 347 Flash Memory Array and Control Table 12-12. PFlash Access Protection Register (PFAPR) Field Descriptions (continued) Field Description SHSACC[7:4] Shadow Block Supervisor Access Control. This bit field defines supervisor/user mode access control for each 4 KB sector within the shadow block region of the flash array. 0 Shadow block sector n can be accessed in both user and supervisor mode.
Page 348 Flash Memory Array and Control Table 12-13. PFlash Supervisor Access Control Register (PFSACC) Field Descriptions Field Description SACC[30:0] Supervisor Access Control. This bit field defines supervisor/user mode access control for each sector within the main flash array. 0 Flash array sector n can be accessed in both user and supervisor mode. 1 Flash array sector n can be accessed only in supervisor mode.
Page 349 Flash Memory Array and Control Table 12-14. {S,D}ACC Register to Flash Array Mapping Starting Flash Sector Size Register Bit Array Address xACC[28] 0x34_0000 256 KB xACC[29] 0x38_0000 256 KB xACC[30] 0x3C_0000 256 KB xACC[31] Reserved 12.3.2.11 PFlash Data Access Control Register (PFDACC) Offset: FLASH_REGS_BASE + 0x002C Access: User read/write DACC[30:16]...
Page 350 Flash Memory Array and Control Offset: FLASH_REGS_BASE + 0x003C Access: User read/write UTE SCBE Reset Reset Figure 12-14. User Test Register 0 (UT0) Table 12-16. UT0 Field Descriptions Field Description UTest Enable. This status bit gives indication when UTest is enabled. All bits in UT0, UT1, UT2, UM0, UM1, UM2, UM3, and UM4 are locked when this bit is 0.
Page 351 Flash Memory Array and Control Table 12-16. UT0 Field Descriptions (continued) Field Description Array Integrity Sequence. AIS determines the address sequence to be used during array integrity checks. The default sequence (AIS = 0) is meant to replicate sequences normal “user” code follows, and thoroughly checks the read propagation paths.
Page 352 Flash Memory Array and Control 12.3.2.14 User Test Register 2 (UT2) Offset: FLASH_REGS_BASE + 0x0044 Access: User read/write Reset Reset Figure 12-16. User Test Register 2 (UT2) Table 12-18. UT2 Field Descriptions Field Description Data Array Input. These bits enable checks of ECC logic by allowing data bits to be input into the ECC logic [63:32] and then read out by doing array reads or array integrity checks.
Page 353 Flash Memory Array and Control Offset FLASH_REGS_BASE + 0x0054 Access: User read/write 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MISR[127:96] Reset 0 0 0 0 Figure 12-20.
Page 354 Flash Memory Array and Control • The read state is active when PGM = 1 or ERS = 1 in the MCR and high-voltage operation is ongoing (read-while-write). NOTE Reads done to the partition(s) being operated on (either erased or programmed) result in an error and the RWE bit in the MCR is set.
Page 355 Flash Memory Array and Control Whenever a program operation occurs, ECC bits are programmed. ECC is handled on a 64-bit boundary. Thus, if only one word in any given 64-bit ECC segment is programmed, the adjoining word (in that segment) should not be programmed because ECC calculation has already completed for that 64-bit segment.
Page 356 Flash Memory Array and Control While MCR[DONE] is low, MCR[EHV] is high, and MCR[PSUS] is low, the user may clear MCR[EHV], resulting in a program abort. A program abort forces the module to step 8 of the program sequence. An aborted program results in MCR[PEG] being set low, indicating a failed operation.
Page 357 Flash Memory Array and Control User mode read state Erase suspend Write MCR Step 1 PGM = 1 Step 2 Program write Last write Step 3 PGM = 0 User mode read state Step 4 Write MCR or erase suspend EHV = 1 WRITE Step 5...
Page 358 Flash Memory Array and Control 12.4.1.3.1 Software Locking A software mechanism is provided to independently lock/unlock each high-, mid-, and low-address space against program and erase. Software locking is done through the LML (low-/mid-address space block locking register), SLL (secondary low-/mid-address space block locking register), or HBL (high-address space block locking register).
Page 359 Flash Memory Array and Control 3. Write to any address in flash. This is referred to as an erase interlock write. 4. Write a logic 1 to the MCR[EHV] bit to start an internal erase sequence or skip to step 9 to terminate.
Page 360 Flash Memory Array and Control The erase operation is resumed by clearing the MCR[ESUS] bit. The flash continues the erase sequence from one of a set of predefined points. This can extend the time required for the erase operation. CAUTION In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt flash core data.
Page 361 Flash Memory Array and Control 12.4.2 UTest Mode UTest mode is a mode that customers can put the flash module in to do specific tests to check the integrity of the Flash module. 12.4.2.1 Array Integrity Self Check Array integrity is checked using a pre-defined address sequence (based on UT0[AIS]), and this operation is executed on selected and unlocked blocks.
Page 362 Flash Memory Array and Control 5. Set the UT0[AIE] bit. If desired, the Array Integrity operation may be aborted prior to UT0[AID] going high. This may be done by clearing the UT0[AIE] bit and then continuing to the next step. It should be noted that in the event of an aborted array integrity check the MISR registers will contain a signature for the portion of the operation that was completed prior to the abort, and will not be deterministic.
Page 363 Flash Memory Array and Control done by clearing the UT0[AIE] bit and then continuing to the next step. It should be noted that in the event of an aborted margin read, the MISR registers contain a signature for the portion of the operation that was completed prior to the abort, but it is not deterministic.
Page 364 Flash Memory Array and Control per 64 bit ECC segment between erases. Erase of the shadow row is done similarly as an array erase. See section Section 12.4.1.4, Flash Erase, for more information. 12.4.4 Flash Sleep Mode Flash sleep mode is entered by setting the FDIS bit in the CPR_SOCSC register. See Section 6.2.2.12, SoC Status and Control Register (CRP_SOCSC), for more information.
Page 365 Chapter 13 e200z6 Core (Z6) 13.1 Introduction The core complex of the PXN20 device consists of the following: • e200z650n3e core described in this chapter • 32 KB unified cache memory • 32-entry memory management unit (MMU) • Nexus class 3 block •...
Page 366 e200z6 Core (Z6) OnCE/NEXUS 1/ Signal NEXUS 3 Control Logic Processing Control Logic Engine (SPE APU) Memory Integer Management Execution GPRs Unit Unit (64-bit) Multiply Instruction Unit Control Unit Instruction Buffer Unified Cache Address 32 KB Data In Branch Data Out Unit Unit Load/...
Page 367 e200z6 Core (Z6) Most integer instructions execute in a single-clock cycle. Branch target prefetching is performed by the branch target address cache to allow single-cycle branches in many cases. The e200z6 core complex is built on a single-issue, 32-bit Power Architecture design with 64-bit general-purpose registers (GPRs).
Page 368 e200z6 Core (Z6) — Support for the wait instruction to halt synchronous activity and/or signal intent to enter low power mode to the CRP. 13.1.3.1 Instruction Unit Features The features of the instruction unit are the following: • 64-bit path to cache supports fetching of two 32-bit instructions per clock, or as many as four 16-bit VLE APU instructions per clock •...
Page 369 e200z6 Core (Z6) 13.1.3.5 L1 Cache Features The features of the cache are as follows: • 32 KB, 4- or 8-way set associative unified cache • Copyback and writethrough support • Eight-entry store buffer • Push buffer • Linefill buffer •...
Page 370 e200z6 Core (Z6) Memory load and store operations are provided for byte, halfword, word (32-bit), and doubleword data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations.
Page 371 e200z6 Core (Z6) Exception Handling/Control Registers General Registers Save and Restore Interrupt Vector Prefix SPR General Condition Register General-Purpose SPRG0 SPR 272 IVPR SPR 63 SRR0 SPR 26 Registers SPRG1 SPR 273 SRR1 SPR 27 Interrupt Vector Offset GPR0 Count Register SPRG2 SPR 274 CSRR0...
Page 372 e200z6 Core (Z6) PXN20 Microcontroller Reference Manual, Rev. 1 13-8 Freescale Semiconductor...
Page 373 e200z6 Core (Z6) USER Mode Programmer’s Model General Registers Timers Cache Registers Condition Register General Purpose Registers Time Base (read-only) Cache Configuration (read-only) GPR0 SPR 268 Count Register GPR1 SPR 269 SPR 515 L1CFG0 SPR 9 Control Registers Link Register SPR General (read-only) GPR31 APU Registers...
Page 374 e200z6 Core (Z6) Figure 13-3. User Mode Programmer’s Model 13.2.1 Power Architecture Registers The e200z6 core supports most of the registers defined by the Power Architecture embedded category. Notable exceptions are the floating point registers FPR0–FPR31 and FPSCR. The e200z6 does not support the Power Architecture floating point architecture in hardware.
Page 375 e200z6 Core (Z6) • Processor control registers — Machine state register (MSR). The MSR defines the state of the processor. The MSR can be modified by the move to machine state register (mtmsr), system call (sc), and return from exception (rfi, rfci, rfdi) instructions. It can be read by the move from machine state register (mfmsr) instruction.
Page 376 e200z6 Core (Z6) — Debug control registers (DBCR0–DBCR2). These registers provide control for enabling and configuring debug events. — Debug status register (DBSR). This register contains debug event status. — Instruction address compare registers (IAC1–IAC4). These registers contain addresses and/or masks which are used to specify instruction address compare debug events.
Page 377 e200z6 Core (Z6) 13.2.2.2 Supervisor-Level Registers The following supervisor-level registers are defined in the e200z6 core in addition to the Power Architecture embedded category registers described previously: • Configuration registers — Hardware implementation-dependent 0 (HID0) controls processor and system functions. —...
Page 378 e200z6 Core (Z6) 13.2.3 e200z6 Core Complex Features Not Supported in the Device The device implements a subset of the e200z6 core complex features. The e200z6 core complex features that are not supported in the device are described in Table 13-2.
Page 379 e200z6 Core (Z6) 13.3.1.1 Translation Lookaside Buffer (TLB) The TLB consists of a 32-entry, fully associative content addressable memory (CAM) array. To perform a lookup, the CAM is searched in parallel for a matching TLB entry. The contents of this TLB entry are then concatenated with the page offset of the original effective address.
Page 380 e200z6 Core (Z6) TLB_entry[V] TLB entry Hit TLB_entry[TS] AS (from MSR[IS] or MSR[DS]) Process ID private page shared page TLB_entry[TID] TLB_entry[EPN] EA page number bits Figure 13-4. Virtual Address and TLB-Entry Compare Process 13.3.1.3 Effective to Real Address Translation Instruction accesses are generated by sequential instruction fetches or due to a change in program flow (branches and interrupts).
Page 381 e200z6 Core (Z6) example, program code might be execute-only and data structures can be mapped as read/write/no-execute. The UX, SX, UW, SW, UR, and SR access control bits support selective permissions for access control: • SR—Supervisor read permission. Allows loads and load-type cache management instructions to access the page while in supervisor mode.
Page 382 e200z6 Core (Z6) 13.3.1.5.1 MAS[0] Register The MAS[0] register is shown in Figure 13-7. SPR: 624 Access: Read/write 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 —...
Page 383 e200z6 Core (Z6) Table 13-5. MAS[1]—Descriptor Context and Configuration Control (continued) Field Description Translation address space. This bit is compared with the IS or DS fields of the MSR (depending on the type of access) to determine if this TLB entry can be used for translation.
Page 384 e200z6 Core (Z6) Table 13-6. MAS[2]—EPN and Page Attributes (continued) Field Description Guarded. The e200z6 ignores the guarded attribute because no speculative or out-of-order processing is performed. 0 Access to this page are not guarded, and can be performed before it is known if they are required by the sequential execution model.
Page 385 e200z6 Core (Z6) Table 13-8. MAS[4]—Hardware Replacement Assist Configuration Register Field Description TLBSELD Default TLB selected 01 TLB1 (ignored by the e200z6, write as 01 for future compatibility) TIDSELD Default PID# to load TID from 00 PID0 01 Reserved, do not use 10 Reserved, do not use 11 TIDZ (0x00)) (Use all zeros, the globally shared value) TSIZED...
Page 386 e200z6 Core (Z6) match a valid cache tag entry (misses in the cache) or a write access must be written through to memory, the cache performs a bus cycle on the system bus. Figure 13-13 shows a block diagram of the unified cache in the e200z6.
Page 387 e200z6 Core (Z6) Way 0 Way 1 Way 2 Way 7 Set 0 Set 1 • • • • • • • • • • • • • • • • • • • Set 126 Line Set 127 Cache line format Doubleword 1 Doubleword 0 Doubleword 2...
Page 388 e200z6 Core (Z6) The cache must be invalidated after a hardware reset; a hardware reset does not invalidate the cache lines. Following initial power-up, the cache contents are undefined. If the L, D, or V bits are set on any lines, the software must invalidate cache before the cache is enabled.
Page 389 e200z6 Core (Z6) 4. Virtual address bits A[27:28] are used to select one of the four doublewords in each line. A cache hit indicates that the selected doubleword in that cache line contains valid data (for a read access), or can be written with new data depending on the status of the W access control bit from the MMU (for a write access).
Page 390 e200z6 Core (Z6) The correct sequence necessary to change the value of LSCSR0 is as follows: 1. msync 2. isync 3. mtspr L1CSR0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 1010;...
Page 391 e200z6 Core (Z6) Table 13-10. L1CSR0 Field Descriptions (continued) Bits Name Description Additional ways data disable. 0 Additional ways beyond 0–3 are available for replacement by data miss line fills. AWDD 1 Additional ways beyond 0–3 are not available for replacement by data miss line fills. For the 32KB 8-way cache, ways 4–7 are considered additional ways.
Page 392 e200z6 Core (Z6) Table 13-10. L1CSR0 Field Descriptions (continued) Bits Name Description 24–26 — Reserved Cache organization 0 The cache is organized as 128 sets and 8 ways CORG 1 The cache is organized as 256 sets and 4 ways. Selecting CORG = 1 helps minimize power consumption.
Page 393 e200z6 Core (Z6) Table 13-11. L1CFG0 Field Descriptions Bits Name Description Cache architecture 0–1 CARCH 01 The cache architecture is unified Cache way partitioning available CWPA 1 The cache supports partitioning of way availability for I/D accesses Cache flush all by hardware available CFAHA 0 The cache does not support flush all in hardware Cache flush/invalidate by set and way available...
Page 394 e200z6 Core (Z6) Table 13-12. Interrupts and Conditions (continued) Core Register Interrupt in Which Interrupt Type Vector Offset Enables State Causing Conditions Register Information is Saved Machine check IVOR 1 CSSR[0:1] • Machine check exception and MSR[ME] = 1 • ISI, ITLB error on first instruction fetch for an exception handler •...
Page 395 e200z6 Core (Z6) Table 13-12. Interrupts and Conditions (continued) Core Register Interrupt in Which Interrupt Type Vector Offset Enables State Causing Conditions Register Information is Saved Debug IVOR 15 DE, IDM CSSR[0:1] Debugger when HIDO[DAPUEN] = 0. Caused by trap, instruction address compare, data address compare, instruction complete, branch taken, return from interrupt, interrupt taken, debug counter, external debug event,...
Page 396 e200z6 Core (Z6) • Decrementer register (DEC)—a decrementing counter that is updated at the same rate as the time base. The DEC provides a means of signaling an exception after a specified amount of time. The DEC is typically used as a general-purpose software timer. Note that the decrementer always runs when the system is clocked, and can be written to by software at any time.
Page 397 e200z6 Core (Z6) The e200z6 core has a 64-bit architectural accumulator register that holds the results of the SPE multiply accumulate (MAC) fixed-point instructions. The accumulator allows back-to-back execution of dependent fixed-point MAC instructions, something that is found in the inner loops of DSP code such as filters. The accumulator is partially visible to the programmer in that its results do not have to be explicitly read to use them.
Page 398 e200z6 Core (Z6) 13.5 External References In addition to the Power Architecture instructions, the device supports e200z6 core-specific instructions and SPE APU instructions and VLE instructions. For further information see the following documents: • e200z6 PowerPC Core Reference Manual • PowerPC Microprocessor Family: The Programming Environment for 32-bit Microprocessors •...
Page 399 Chapter 14 e200z0 Core (Z0) 14.1 Introduction The e200 processor family is a set of CPU cores that implement low-cost versions of the Power Architecture Book E architecture. e200 processors are designed for deeply embedded control applications that require low cost solutions rather than maximum performance. The e200z0 processors integrate an integer execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported register file capable of sustaining three read and two write operations per clock.
Page 400 e200z0 Core (Z0) — 1 cycle load latency — Fully pipelined — Big-endian support only — Misaligned access support — Zero load-to-use pipeline bubbles for aligned transfers • Power management — Low power design — Power saving modes: doze, nap, sleep, and wait —...
Page 401 e200z0 Core (Z0) dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases. The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture.
Page 402 e200z0 Core (Z0) • Dedicated PC incrementer supporting instruction prefetches • Branch unit with dedicated branch address adder supporting single cycle of execution of certain branches, two cycles for all others 14.2.2 Integer Unit Features The e200 integer unit supports single cycle execution of most integer instructions: •...
Page 403 e200z0 Core (Z0) • Run-time access to the processor memory map via the JTAG port. This allows for enhanced download/upload capabilities. • Watchpoint messaging through the auxiliary interface. • Watchpoint trigger enable of program trace messaging. • Auxiliary interface for higher data input/output (Nexus interface shared with Z6 core). —...
Page 404 e200z0 Core (Z0) SUPERVISOR Mode Program Model Exception Handling/Control Registers General Registers Save and Restore Interrupt Vector Prefix SPR General Condition Register General-Purpose SPRG0 SPR 272 IVPR SPR 63 SRR0 SPR 26 Registers SPRG1 SPR 273 SRR1 SPR 27 GPR0 Count Register CSRR0 SPR 58...
Page 405 e200z0 Core (Z0) USER Mode Programmer Model General Registers General-Purpose Condition Register Registers Cache Registers GPR0 Count Register Cache Configuration GPR1 (Read-only) SPR 9 Link Register L1CFG0 SPR 515 SPR 8 GPR31 SPR 1 Figure 14-3. e200 User Mode Program Model General purpose registers (GPRs) are accessed through instruction operands.
Page 406 e200z0 Core (Z0) Integer exception register (XER). The XER indicates overflow and carries for integer operations. See XER Register (XER), in Chapter 4, nteger Operations, of Power Architecture Book E Specification for more information. • Link register (LR). The LR provides the branch target address for the Branch to Link Register ) instructions, and is used to hold the address of the instruction that follows a branch se_blr se_blrl...
Page 407 e200z0 Core (Z0) — SPRG0–SPRG1. The SPRG0–SPRG1 registers are provided for operating system or interrupt handler use. — Exception Syndrome Register (ESR). The ESR register provides a syndrome to differentiate between the different kinds of exceptions which can generate the same interrupt. —...
Page 408 e200z0 Core (Z0) 14.3.2.2 Supervisor-Level Registers The following supervisor-level registers are defined in e200 in addition to the Power Architecture Book E registers described above: • Configuration Registers — Hardware implementation-dependent register 0 (HID0). This register controls various processor and system functions. —...
Page 409 e200z0 Core (Z0) 14.3.3 e200z0 Core Complex Features not Supported on the PXN20 The PXN20 implements a subset of the e200z0 core complex features. The e200z0 core complex features that are not supported in the PXN20 are described in Table 14-2.
Page 410 e200z0 Core (Z0) Table 14-3. Exceptions and Conditions (continued) Interrupt Vector Interrupt Type Causing Conditions Offset Register AP unavailable IVOR 9 Unused Decrementer IVOR 10 Unused Fixed Interval IVOR 11 Unused Timer Watchdog Timer IVOR 12 Unused Data TLB Error IVOR 13 Unused Instruction TLB...
Page 411 e200z0 Core (Z0) 14.5 Bus Interface Unit (BIU) The BIU encompasses control and data signals supporting instruction and data transfers, support for interrupts, including vectored interrupt logic, reset support, power management interface signals, debug event signals, processor state information, Nexus /OnCE / JTAG interface signals, and a test interface. The memory portion of the e200 core interface is comprised of a 32-bit wide system bus and a unified bus.
Page 412 e200z0 Core (Z0) PXN20 Microcontroller Reference Manual, Rev. 1 14-14 Freescale Semiconductor...
Page 413 Chapter 15 Semaphores 15.1 Introduction In a dual processor chip, semaphores are used to let each processor know who has control of common memory. Before a core can update or read memory coherently, it has to check the semaphore to see if the other core is not already updating the memory.
Page 414 Semaphores aips_master ips_wdata master_eq_cp{0,1} wdata_eq_{unlock, cp[0-1]_lock} ips_addr decode gate0 gate1 gate2 gate3 control gate12 gate13 gate14 gate15 ips_rdata cp0_semaphore_int cp1_semaphore_int IPS Bus Figure 15-1. Semaphores Block Diagram 15.1.2 Features The semaphores module implements hardware-enforced semaphores as a peripheral device and has these major features: •...
Page 415 Semaphores if gate = 0b01, then state = locked by e200z6 (master ID = 0) if gate = 0b10, then state = locked by e200z0 (master ID = 1) – Uses the bus master ID number as a reference attribute plus the specified data patterns to validate all write operations –...
Page 416 Semaphores Table 15-1. Semaphores Memory Map (continued) Offset from Section/ SEMA4_BASE Register Access Reset Value Page (0xFFF1_0000) 0x0007 SEMA4_Gate07—Semaphores gate 7 0x00 15.3.2.1/15-4 0x0008 SEMA4_Gate08—Semaphores gate 8 0x00 15.3.2.1/15-4 0x0009 SEMA4_Gate09—Semaphores gate 9 0x00 15.3.2.1/15-4 0x000A SEMA4_Gate10—Semaphores gate 10 0x00 15.3.2.1/15-4 0x000B SEMA4_Gate11—Semaphores gate 11...
Page 417 Semaphores Multiple gate values can be read in a single access, but only a single gate at a time can be updated via a write operation. 16- and 32-bit writes to multiple gates are allowed, but the write data operand must update the state of a single gate only.
Page 418 Semaphores Table 15-3. SEMA4_CP{0,1}NTF Field Descriptions Field Description INEn Interrupt Request Notification Enable n. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate n. 0 The generation of the notification interrupt is disabled. 1 The generation of the notification interrupt is enabled.
Page 419 Semaphores watchdog timer, the secure gate reset requires two consecutive writes with predefined data patterns from the same processor to force the clearing of the specified gate(s). The required access pattern is: 1. A processor performs a 16-bit write to the SEMA4_RSTGT memory location. The most significant byte (SEMA4_RSTGT[RSTGDP]) must be 0xE2;...
Page 420 Semaphores Table 15-5. SEMA4_RSTGT Field Descriptions Field Description RSTGSM Reset Gate Finite State Machine. The reset state machine is maintained in a 2-bit, three-state implementation, defined as: 00 Idle, waiting for the first data pattern write. 01 Waiting for the second data pattern write. 10 The 2-write sequence has completed.
Page 421 Semaphores reset mechanism requires two consecutive writes with predefined data patterns from the same processor to force the clearing of the IRQ notification(s). The required access pattern is: 1. A processor performs a 16-bit write to the SEMA4_RSTNTF memory location. The most significant byte (SEMA4_RSTNTF[RSTNDP]) must be 0x47;...
Page 422 Semaphores Table 15-6. SEMA4_RSTGT Field Descriptions Field Description RSTNSM Reset Notification Finite State Machine. The reset state machine is maintained in a 2-bit, three-state implementation, defined as: 00 Idle, waiting for the first data pattern write. 01 Waiting for the second data pattern write. 10 The two-write sequence has completed.
Page 423 Semaphores processes/processors are locked out. Many software implementations include a spin-wait loop within the lock function until the locking of the gate is accomplished. After the lock has been obtained, processor X continues execution and updates the data values protected by the particular lock. After the updates are complete, processor X unlocks (or opens) the software gate, allowing other processes/processors access to the updated data values.
Page 424 Semaphores 15.4.1 Semaphore Usage Example 1: Inter-processor communication done with software interrupts and semaphores... • The Z0 uses software interrupts to tell the Z6 that new data is available, or the Z6 does the same to tell the Z0 that there is new data available for transmission. •...
Page 425 Semaphores • To lock (close) a gate — The processor performs a byte write of logical_processor_number + 1 to gate[i] — The processor reads back gate[i] and checks for a value of logical_processor_number + 1 If the compare indicates the expected value then the gate is locked;...
Page 426 Semaphores cores. The exact method for accessing the logical processor number varies by architecture. For Power Architecture cores, there is a processor ID register (PIR) which is SPR 286 and contains this value. A single instruction can be used to move the contents of the PIR into a general-purpose register: mfspr rx,286 where rx is the destination GPRn.
Page 427 Chapter 16 AMBA Crossbar Switch (AXBS) 16.1 Introduction This chapter describes the multi-port crossbar switch (AXBS), which supports simultaneous connections between six master ports and six slave ports. The AXBS supports a 32-bit address bus width and a 64-bit data bus width at all master and slave ports. 16.1.1 Block Diagram Figure 16-1...
Page 428 AMBA Crossbar Switch (AXBS) Table 16-1. Master Assignments and Master IDs AXBS Port AXBS Module Master ID Off Platform (FlexRay) Z0 Core The AXBS supports six slaves running at system frequency. The slave data bus width is 64 bits. Table 16-2 summarizes the crossbar slave port assignments.
Page 429 AMBA Crossbar Switch (AXBS) • Six slave ports — Flash port dedicated to Z6 core — Flash port for all other masters (refer to Chapter 12, Flash Memory Array and Control, information on accessing flash memory) — 512K SRAM at address 0x4000_0000 —...
Page 430 AMBA Crossbar Switch (AXBS) Table 16-3. AXBS Register Memory Map (continued) Offset from AXBS_BASE Register Access Reset Value Section/Page (0xFFF0_4000) 0x0204–0x020F Reserved 0x0210 XBAR_SGPCR2—General-Purpose Control Register, Slave 0x0000_0000 16.2.1.2/16-6 Port 2 0x0214–0x02FF Reserved 0x0300 XBAR_MPR3—Master Priority Register, Slave Port 3 0x5400_3210 16.2.1.1/16-4 0x0304–0x030F...
Page 431 AMBA Crossbar Switch (AXBS) NOTE Masters must be assigned unique priority levels. The master priority register can only be accessed in supervisor mode with 32-bit accesses. After the read only (RO) bit is set in the slave general-purpose control register, the master priority register can only be read.
Page 432 AMBA Crossbar Switch (AXBS) Table 16-4. XBAR_MPRn Descriptions (continued) Field Description MSTR2 Master 2 priority. Set the arbitration priority for master port 2 on the associated slave port. This master has the highest priority when accessing the slave port. 101 This master has the lowest priority when accessing the slave port. 110–111 Invalid values MSTR1...
Page 433 AMBA Crossbar Switch (AXBS) Address: AXBS_BASE + 0x0010 (XBAR_SGPCR0) AXBS_BASE + 0x0310 (XBAR_SGPCR3) AXBS_BASE + 0x0110 (XBAR_SGPCR1) AXBS_BASE + 0x0610 (XBAR_SGPCR6) AXBS_BASE + 0x0210 (XBAR_SGPCR2) AXBS_BASE + 0x0710 (XBAR_SGPCR7) Access: Supervisor read/write Reset PCTL PARK Reset After this bit is set, only a hardware reset clears it. Figure 16-3.
Page 434 AMBA Crossbar Switch (AXBS) 16.2.1.3 Master General Purpose Control Registers (XBAR_MGPCRn) The Master General Purpose Control Register (XBAR_MGPCR) controls the arbitration policy during undefined length burst accesses. The AULB (Arbitrate on Undefined Length Bursts) field determines whether or not arbitration occurs for the slave port the master owns when the master is performing undefined length burst accesses.
Page 435 AMBA Crossbar Switch (AXBS) 16.3.2 General Operation When a master makes an access to the AXBS from an idle master state, the access is taken immediately by the AXBS. If the targeted slave port of the access is available (that is, the requesting master is currently granted ownership of the slave port), the access is immediately presented on the slave port.
Page 436 AMBA Crossbar Switch (AXBS) requesting masters, then the master gains control over the slave port as soon as the data phase of the current access is completed. If the slave port is currently servicing another master of a higher priority, then the master gains control of the slave port after the other master releases control of the slave port if no other higher priority master is also waiting for the slave port.
Page 437 AMBA Crossbar Switch (AXBS) If the new requesting master’s priority level is higher than that of the master that currently has control of the slave port, the higher priority master is granted control at the termination of any currently pending access, assuming the pending transfer is not part of a burst transfer.
Page 438 AMBA Crossbar Switch (AXBS) 16.3.6.2.1 Parking If no master is currently requesting the slave port, the slave port is parked. The slave port parks in one of three places, indicated by the value of the PCTL field in the XBAR_SGPCR. •...
Page 439 Chapter 17 Peripheral Bridge (AIPS-lite) 17.1 Introduction The AIPS-lite acts as an interface between the system bus and lower bandwidth peripherals. 17.1.1 Block Diagram A simplified block diagram of the AIPS-lite illustrates the functionality and interdependence of major blocks (see Figure 17-1).
Page 440 Peripheral Bridge (AIPS-lite) 17.1.3 Modes of Operation The AIPS-lite has only one operating mode. 17.2 External Signal Description The AIPS-lite has no external signals. 17.3 Memory Map and Register Description The AIPS-lite does not contain any user-programmable registers. 17.4 Functional Description The AIPS-lite serves as an interface between an AHB 2.v6 system bus and the peripheral interface bus.
Page 441 Chapter 18 Memory Protection Unit (MPU) 18.1 Introduction The memory protection unit (MPU) provides hardware access control for all memory references generated in a device. Using pre-programmed region descriptors that define memory spaces and their associated access rights, the MPU concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer.
Page 442 Memory Protection Unit (MPU) AXBS ports Master Slave Master ID 0 (8 for Nexus) Flash Port 0 (e200z6) e200z6 Master ID 2 eDMA Flash Port 1 Master ID 5 512K SRAM Master ID 4 80K SRAM Master ID 6 AIPS_A FlexRay Master ID 1 AIPS_B...
Page 443 Memory Protection Unit (MPU) — Two types of access control definitions: two processor core bus masters (e200z6 and e200z0) support the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses; the remaining three non-core bus masters (DMA, FlexRay, and AIPS) support {read, write} attributes —...
Page 444 Memory Protection Unit (MPU) Table 18-2. MPU Memory Map Offset from MPU_BASE Register Access Reset Value Section/Page (0xFFF1_4000) 0x0000 MPU_CESR—MPU control/error status register 0x0080_4200 18.3.2.1/18-5 0x0004–0x000F Reserved 0x0010 MPU_EAR0—MPU error address register, MPU port 0 — 18.3.2.2/18-6 0x0014 MPU_EDR0—MPU error detail register, MPU port 0 —...
Page 445 Memory Protection Unit (MPU) Table 18-2. MPU Memory Map (continued) Offset from MPU_BASE Register Access Reset Value Section/Page (0xFFF1_4000) 0x080C MPU_RGDAAC3—MPU RGD alternate access control 3 — 18.3.2.5/18-13 0x0810 MPU_RGDAAC4—MPU RGD alternate access control 4 — 18.3.2.5/18-13 0x0814 MPU_RGDAAC5—MPU RGD alternate access control 5 —...
Page 446 Memory Protection Unit (MPU) Each MPERR bit can be cleared by writing a one to the bit location. Table 18-3. MPU_CESR Field Descriptions Field Description MPERR MPU Port n Error, where the MPU port number matches the bit number. Each bit in this read-only field represents a flag maintained by the MPU for signaling the presence of a captured error contained in the MPU_EARn and MPU_EDRn registers.
Page 447 Memory Protection Unit (MPU) Offset: MPU_BASE + 0x0010 (MPU_EAR0) Access: User read-only MPU_BASE + 0x0018 (MPU_EAR1) MPU_BASE + 0x0020 (MPU_EAR2) MPU_BASE + 0x0028 (MPU_EAR3) EADDR Reset – – – – – – – – – – – – – – –...
Page 448 Memory Protection Unit (MPU) Table 18-5. MPU_EDRn Field Descriptions Field Description EACD Error Access Control Detail. This 16-bit read-only field implements one bit per region descriptor and is an indication of the region descriptor hit logically-ANDed with the access error indication. The MPU performs a reference-by-reference evaluation to determine the presence/absence of an access error.
Page 449 Memory Protection Unit (MPU) Offset: MPU_BASE + 0x400 + (16*n) + 0x0 (MPU_RGDn.Word0) Access: User read/write SRTADDR Reset – – – – – – – – – – – – – – – – SRTADDR Reset – – – – –...
Page 450 Memory Protection Unit (MPU) typically reserved for processor cores. The corresponding access control is a 6-bit field defining separate privilege rights for user and supervisor mode accesses as well as the optional inclusion of a process identification field within the definition. Bus masters 4–7 are typically reserved for data movement engines and their capabilities are limited to separate read and write permissions.
Page 451 Memory Protection Unit (MPU) Table 18-8. MPU_RGDn.Word2 Field Descriptions (continued) Field Description M6WE Bus Master ID 6 Write Enable. If set, this flag allows bus master ID 6 (FlexRay) to perform write operations. If cleared, any attempted write by bus master ID 6 terminates with an access error and the write is not performed. M5RE Bus Master ID 5 Read Enable.
Page 452 Memory Protection Unit (MPU) Table 18-8. MPU_RGDn.Word2 Field Descriptions (continued) Field Description M0UM Bus Master ID 0 User Mode Access Control. This 3-bit field defines the access controls for bus master ID 0 (e200z6) when operating in user mode. The M0UM field consists of three independent bits, enabling read, write, and execute permissions: {r,w,x}.
Page 453 Memory Protection Unit (MPU) Table 18-9. MPU_RGDn.Word3 Field Descriptions Field Description Process Identifier. This 8-bit field specifies that the optional process identifier is to be included in the determination of whether the current access hits in the region descriptor. This field is combined with the PIDMASK and included in the region hit determination if MPU_RGDn.Word2[MxPE] is set.
Page 454 Memory Protection Unit (MPU) Table 18-10. MPU_RGDAACn Field Descriptions Field Description M6RE Bus Master ID 6 Read Enable. If set, this flag allows bus master ID (FlexRay) 6 to perform read operations. If cleared, any attempted read by bus master ID 6 terminates with an access error and the read is not performed. M6WE Bus Master ID 6 Write Enable.
Page 455 Memory Protection Unit (MPU) Table 18-10. MPU_RGDAACn Field Descriptions (continued) Field Description M0SM Bus Master 0 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master ID 0 (e200z6) when operating in supervisor mode. The M0SM field is defined as: 00 r, w, x = read, write and execute allowed.
Page 456 Memory Protection Unit (MPU) 18.4.1.1 Access Evaluation—Hit Determination To determine if the current AHB reference hits in the given region, two magnitude comparators are used with the region’s start and end addresses. The boolean equation for this portion of the hit determination is defined as: region_hit = ((haddr[0:26] >= rgdn.srtaddr[0:26]) &...
Page 457 Memory Protection Unit (MPU) The resulting boolean equation for the processor protection violations is: cpu_protection_violation = ~hwrite & ~hprot[0] & ~eff_rgdn[x] // ifetch & no x | ~hwrite & hprot[0] & ~eff_rgdn[r] // data_read & no r hwrite & ~eff_rgdn[w] // data_write &...
Page 458 Memory Protection Unit (MPU) Typically the appropriate number of region descriptors (MPU_RGDn) are loaded at system startup, including the setting of the MPU_RGDn.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the module. This approach allows all the loaded region descriptors to be enabled simultaneously. If a memory reference does not hit in any region descriptor, the attempted access is terminated with an error.
Page 459 Memory Protection Unit (MPU) 7. Finally, consider the use of overlapping region descriptors. Application of overlapping regions can reduce the number of descriptors required for a given set of access controls. In the overlapping memory space, the protection rights of the corresponding region descriptors are logically summed together (the boolean OR operator).
Page 460 Memory Protection Unit (MPU) PXN20 Microcontroller Reference Manual, Rev. 1 18-20 Freescale Semiconductor...
Page 461 Chapter 19 Error Correction Status Module (ECSM) 19.1 Introduction The error correction status module (ECSM) provides a set of registers that configure and report ECC errors for the device including accesses to RAM and flash memory. The application may configure the device for the types of memory errors to be reported, and then query a set of read-only status and information registers to identify any errors that have been signaled.
Page 462 Error Correction Status Module (ECSM) 19.2.1 Module Memory Map The ECSM memory map is shown in Table 19-1 (a graphical layout of the registers is shown in Table 19-2 to better see Reserved areas in the memory map). The address of each register is given as an offset to the ECSM base address.
Page 463 Error Correction Status Module (ECSM) Table 19-2. ECSM Graphical Memory Map Register ECSM Offset 0x000048 Reserved ECC error generation register (EEGR) 0x004C Reserved 0x0050 PFlash ECC address register (PFEAR) PFlash ECC master PFlash ECC attributes 0x0054 Reserved register (PFEMR) register (PFEAT) 0x0058 Reserved 0x005C...
Page 464 Error Correction Status Module (ECSM) Offset: ECSM_BASE_ADDR + 0x0024 Access: User read/write R FXS RBEN WBEN ACC Reset Reset Figure 19-1. FEC Burst Optimization Master Control Register (FBOMCR) Table 19-3. FBOMCR Field Descriptions Field Description FXSBEn FEC XBAR slave burst enable. FXSBEn enables bursting by the FEC interface to the XBAR slave port [0:7] controlled by that respective FXSBEn bit.
Page 465 Error Correction Status Module (ECSM) 19.2.2.2 ECC Configuration Register (ECR) The ECC configuration register is an 8-bit control register for specifying which types of memory errors are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access to be terminated with an error condition.
Page 466 Error Correction Status Module (ECSM) 19.2.2.3 ECC Status Register (ESR) The ECC status register is an 8-bit control register for signaling which types of properly enabled ECC events have been detected. The ESR signals the last properly enabled memory event to be detected. An ECC interrupt request is asserted if any flag bit is asserted and its corresponding enable bit is asserted.
Page 467 Error Correction Status Module (ECSM) Table 19-5. ESR Field Descriptions (continued) Field Description PRNCE Platform RAM Non-Correctable Error. The occurrence of a properly enabled non-correctable RAM error generates an ECSM ECC interrupt request. The faulting address, attributes, and data in either the 512K or 80K array are also captured in the PREAR, PRESR, PREMR, PREAT, and PREDR registers.
Page 468 Error Correction Status Module (ECSM) Table 19-6. EEGR Field Descriptions Field Description FRC1BI Force Platform RAM Continuous 1-Bit Data Inversions. The assertion of this bit forces the platform RAM controller to create 1-bit data inversions, as defined by the bit position specified in ERRBIT[6:0], continuously on every write operation.
Page 469 Error Correction Status Module (ECSM) Table 19-6. EEGR Field Descriptions (continued) Field Description PREI_SEL Platform RAM Error Injection Select. Platform RAM Error Injection Select. The platform contains two platform RAM blocks with ECC. This bit selects which RAM is injected. 0 PRAM0 is injected.
Page 470 Error Correction Status Module (ECSM) Offset: ECSM_BASE_ADDR + 0x0050 Access: User read-only PFEAR Reset PFEAR Reset Figure 19-5. Platform Flash ECC Address (PFEAR) Register Table 19-7. PFEAR Field Descriptions Field Description PFEAR Platform Flash ECC Address Register. Contains the faulting access address of the last properly enabled platform flash ECC event.
Page 471 Error Correction Status Module (ECSM) ECC event in the platform flash causes the address, attributes and data associated with the access to be loaded into the PFEAR, PFEMR, PFEAT, and PFEDR registers and also the appropriate flag (PF1BC or PFNCE) in the ECC status register to be asserted. This register is read-only;...
Page 472 Error Correction Status Module (ECSM) Offset: ECSM_BASE_ADDR + 0x0058 Access: User read-only PFEDR[0:15] Reset PFEDR[16:31] Reset Figure 19-8. Platform Flash ECC Data High (PFEDRH) Register Offset: ECSM_BASE_ADDR + 0x005C Access: User read-only PFEDR[32:47] Reset PFEDR[48:63] Reset Figure 19-9. Platform Flash ECC Data Low (PFEDRL) Register Table 19-10.
Page 473 Error Correction Status Module (ECSM) Offset: ECSM_BASE_ADDR + 0x0060 Access: User read-only PREAR Reset PREAR Reset Figure 19-10. Platform RAM ECC Address (PREAR) Register Table 19-11. PREAR Field Descriptions Field Description PREAR Platform RAM ECC Address Register. Contains the faulting access address of the last properly enabled platform RAM ECC event.
Page 474 Error Correction Status Module (ECSM) Table 19-13. Platform RAM Syndrome Mapping for Single-Bit Correctable Errors PRESR[0:7] Data Bit in Error PRESR[0:7] Data Bit in Error PRESR[0:7] Data Bit in Error 0x00 No Error 0x4F DATA[32] 0xA4 DATA[41] 0x01 ECC[0] 0x52 DATA[34] 0xA7 DATA[42]...
Page 475 Error Correction Status Module (ECSM) Offset: ECSM_BASE_ADDR + 0x0066 Access: User read-only PREMR Reset Figure 19-12. Platform RAM ECC Master Number (PREMR) Register Table 19-14. PREMR Field Descriptions Field Description PREMR Platform RAM ECC Master Number Register. Contains the AXBS bus master number of the faulting access of the last properly enabled platform RAM ECC event.
Page 476 Error Correction Status Module (ECSM) Table 19-15. PREAT Field Descriptions (continued) Field Description SIZE 000 8-bit access. 001 16-bit access. 010 32-bit access. 011 64-bit access. 1xx Reserved. PROTEC Cache: TION 0xxx Non-cacheable. 1xxx Cacheable. Buffer: x0xx Non-bufferable. x1xx Bufferable. Mode: xx0x User mode.
Page 477 Error Correction Status Module (ECSM) Offset: ECSM_BASE_ADDR + 0x006C Access: User read-only PREDR[32:47 Reset PREDR48:63] Reset Figure 19-15. Platform RAM ECC Data Low (PREDRL) Register Table 19-16. PREDR Field Descriptions Field Description PREDR Platform RAM ECC Data Register. Contains the data associated with the faulting access of the last properly enabled platform RAM ECC event.
Page 478 Error Correction Status Module (ECSM) PXN20 Microcontroller Reference Manual, Rev. 1 19-18 Freescale Semiconductor...
Page 479 Chapter 20 Software Watchdog Timer (SWT) 20.1 Introduction The Software Watchdog Timer (SWT) is a peripheral module that can prevent system lockup in situations such as software getting trapped in a loop or if a bus transaction fails to terminate. When enabled, the SWT requires periodic execution of a watchdog servicing operation.
Page 480 Software Watchdog Timer (SWT) 20.3 Memory Map and Register Definition The SWT programming model has seven 32-bit registers. The programming model can only be accessed using 32-bit (word) accesses. References using a different size are invalid. Other types of invalid accesses include: writes to read-only registers, incorrect values written to the service register when enabled, accesses to reserved addresses and accesses by masters without permission.
Page 481 Software Watchdog Timer (SWT) Offset: SWT_BASE + 0x0000 Access: User read/write R MAP Reset Reset Figure 20-1. SWT Control Register (SWT_CR) Table 20-2. SWT_CR Field Descriptions Field Description MAPn Master Access Protection for Master n. The PXN20 bus master assignments are shown in the following table. 0 Access for the master is not enabled 1 Access for the master is enabled.
Page 482 Software Watchdog Timer (SWT) Table 20-2. SWT_CR Field Descriptions Field Description Soft Lock. This bit is cleared by writing the unlock sequence to the service register. 0 SWT_CR, SWT_TO SWT_WN and SWT_SK are read/write registers if HLK = 0. 1 SWT_CR, SWT_TO, SWT_WN and SWT_SK are read-only registers. Debug Mode Control.
Page 483 Software Watchdog Timer (SWT) Offset: SWT_BASE + 0x0008 Access: User read/write Reset Reset Figure 20-3. SWT Time-Out Register (SWT_TO) Table 20-4. SWT_TO Register Field Descriptions Field Description Watchdog time-out period in clock cycles. An internal 32-bit down counter is loaded with this value or 0x0100, whichever is greater, when the service sequence is written or when the SWT is enabled.
Page 484 Software Watchdog Timer (SWT) 20.3.2.5 SWT Service Register (SWT_SR) The SWT Time-Out (SWT_SR) service register is the target for service operation writes used to reset the watchdog timer. Offset: SWT_BASE + 0x0010 Access: User read/write Reset Reset Figure 20-5. SWT Service Register (SWT_SR) Table 20-6.
Page 485 Software Watchdog Timer (SWT) Table 20-7. SWT_CO Register Field Descriptions Field Description Watchdog Count. When the watchdog is disabled (SWT_CR[WEN] = 0) this field shows the value of the internal down counter. When the watchdog is enabled the value of this field is 0x0000_0000. Values in this field can lag behind the internal counter value for as many as 6 system plus 8 counter clock cycles.
Page 486 Software Watchdog Timer (SWT) The SWT_TO register holds the watchdog time-out period in clock cycles unless the value is less than 0x100, in which case the time-out period is set to 0x100. This time-out period is loaded into an internal 32-bit down counter when the SWT is enabled and each time a valid service operation is performed.
Page 487 Software Watchdog Timer (SWT) to open due to synchronization logic in the watchdog design. This delay could be as many as 3 system plus 4 counter clock cycles. The interrupt then reset bit (SWT_CR[ITR]) controls the action taken when a time-out occurs. If the SWT_CR[ITR] bit is not set, a reset is generated immediately on a time-out.
Page 488 Software Watchdog Timer (SWT) PXN20 Microcontroller Reference Manual, Rev. 1 20-10 Freescale Semiconductor...
Page 489 Chapter 21 System Timer Module (STM) 21.1 Overview The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256).
Page 490 System Timer Module (STM) 21.3 Memory Map and Register Definition The STM has 14 32-bit read and write access registers. The STM registers can only be accessed using 32-bit (word) accesses. Attempted references using a different size or to a reserved address generates a bus error termination.
Page 491 System Timer Module (STM) 21.3.2.1 STM Control Register (STM_CR) The STM Control Register (STM_CR) includes the prescale value, freeze control, and timer enable bits. Offset: STM_BASE + 0x0000 Access: User read/write Reset Reset Figure 21-1. STM Control Register (STM_CR) Table 21-2. STM_CR Field Descriptions Field Description Counter Prescaler.
Page 492 System Timer Module (STM) 21.3.2.3 STM Channel Control Register (STM_CCRn) The STM Channel Control Register (STM_CCRn) is used to enable and service channel n of the timer. Offset STM_CCR0: STM_BASE + 0x0010 Access: User read/write STM_CCR1: STM_BASE + 0x0020 STM_CCR2: STM_BASE + 0x0030 STM_CCR3: STM_BASE + 0x0040 Reset Reset...
Page 493 System Timer Module (STM) Table 21-5. STM_CIRn Field Descriptions Field Description Channel Interrupt Flag. The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect. 0 No interrupt request. 1 Interrupt request due to a match on the channel. 21.3.2.5 STM Channel Compare Register (STM_CMPn) The STM channel compare register (STM_CMPn) holds the compare value for channel n.
Page 494 System Timer Module (STM) PXN20 Microcontroller Reference Manual, Rev. 1 21-6 Freescale Semiconductor...
Page 495 Chapter 22 Periodic Interrupt Timer (PIT) 22.1 Introduction The Periodic Interrupt Timer (PIT) is an array of timers that can be used to initiate interrupts and trigger DMA channels. 22.1.1 Block Diagram A simplified block diagram of the PIT illustrates the functionality and interdependence of major blocks (see Figure 22-1).
Page 496 Periodic Interrupt Timer (PIT) 22.1.2 Features The PIT has these major features: • Eight 32-bit timers generating DMA trigger pulses • All timers can be configured to generate interrupts instead of triggers • Timer 3 can be the source of an ADC trigger input via SIU configuration •...
Page 497 Periodic Interrupt Timer (PIT) Table 22-2. PIT Memory Map Offset from PIT_BASE Register Access Reset Value Section/Page (0xFFFE_0000) 0x0000 PITMCR—PIT Module Control Register 0x0000_0000 22.3.2.1/22-4 0x0004–0x00FF Reserved Timer Channel 1 0x0100 LDVAL1—Timer 1 Load Value Register 0x0000_0000 22.3.2.2/22-5 0x0104 CVAL1—Timer 1 Current Value Register 0x0000_0000 22.3.2.3/22-5 0x0108...
Page 498 Periodic Interrupt Timer (PIT) Table 22-2. PIT Memory Map (continued) Offset from PIT_BASE Register Access Reset Value Section/Page (0xFFFE_0000) Timer Channel 7 0x0160 LDVAL7—Timer 7 Load Value Register 0x0000_0000 22.3.2.2/22-5 0x0164 CVAL7—Timer 7 Current Value Register 0x0000_0000 22.3.2.3/22-5 0x0168 TCTRL7—Timer 7 Control Register 0x0000_0000 22.3.2.4/22-6 0x016C...
Page 499 Periodic Interrupt Timer (PIT) Table 22-3. PITMCR Field Descriptions Field Description MDIS Module Disable. This is used to disable the module clock. This bit should be enabled before any other setup is done. 0 Clock for PIT Timers is enabled. 1 Clock for PIT Timers is disabled (default).
Page 500 Periodic Interrupt Timer (PIT) Offset: Channel_base + 0x0004 Access: User read/write LDVAL1 = 0x0104 LDVAL5 = 0x0144 LDVAL2 = 0x0114 LDVAL6 = 0x0154 LDVAL3 = 0x0124 LDVAL7 = 0x0164 LDVAL4 = 0x0134 LDVAL8 = 0x0174 TVL31 TVL30 TVL29 TVL28 TVL27 TVL26 TVL25 TVL24 TVL23 TVL22 TVL21 TVL20 TVL19 TVL18 TVL17 TVL16 Reset TVL15 TVL14 TVL13 TVL12 TVL11 TVL10 TVL9 TVL8...
Page 501 Periodic Interrupt Timer (PIT) Table 22-6. TCTRLn Field Descriptions Field Description Timer Interrupt Enable Bit. 0 Interrupt requests from Timer n are disabled. 1 Interrupt will be requested whenever TIF is set. When an interrupt is pending (TIF set), enabling the interrupt will immediately cause an interrupt event. To avoid this, the associated TIF flag must be cleared first.
Page 502 Periodic Interrupt Timer (PIT) 22.4 Functional Description The PIT block has eight timers for general-purpose use. Each timer can be used to generate trigger pulses as well as to generate interrupts. Each interrupt is available on a separate interrupt line. 22.4.1 Timers The timers generate triggers at periodic intervals, when enabled.
Page 503 Periodic Interrupt Timer (PIT) Timer Enabled New Start Start Value = p1 Value p2 set Trigger Event Figure 22-9. Dynamically Setting a New Load Value 22.4.2 Debug Mode In debug mode, the timers are frozen. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system (e.g., the timer values), and then continue the operation.
Page 504 Periodic Interrupt Timer (PIT) Timer 8 is used for triggering only. Timer 8 is started by writing a 1 to bit TEN in the TCTRL8 register. The following example code matches the described setup: // turn on PIT PIT_REG_P->pit_CTRL = 0x00; // Timer 1 PIT_REG_P->pit_LDVAL1 = 0x0003E7FF;...
Page 505 Chapter 23 DMA Channel Multiplexer (DMA_MUX) 23.1 Introduction The DMA channel multiplexer (DMA_MUX) module allows for software selection of 32 out of 59 possible DMA sources. As many as 55 of these DMA sources are requests from peripherals, but four of the peripheral sources are reserved and behave as always disabled sources.
Page 506 DMA Channel Multiplexer (DMA_MUX) 23.1.2 Features The DMA_MUX has these major features: • 32 independently selectable DMA channel routers — Four channels with normal or periodic triggering capability — 24 channels with normal operation only — Each channel router can be assigned to 1 of 55 possible peripheral DMA sources, eight always enabled sources, or one always disabled source.
Page 507 DMA Channel Multiplexer (DMA_MUX) CHCONFIG0 through CHCONFIG4 are accessible by a 32-bit READ/WRITE to address DMA_MUX_BASE + 0x00, but performing a 32-bit access to address DMA_MUX_BASE + 0x01 is illegal. Table 23-1. DMA_MUX Memory Map Offset from DMA_MUX_BASE Register Access Reset Value Section/Page (0xFFFD_C000) 0x0000 CHCONFIG0—Channel #0 configuration...
Page 508 DMA Channel Multiplexer (DMA_MUX) Table 23-1. DMA_MUX Memory Map (continued) Offset from DMA_MUX_BASE Register Access Reset Value Section/Page (0xFFFD_C000) 0x001D CHCONFIG29—Channel #29 configuration 0x00 23.3.2.1/23-4 0x001E CHCONFIG30—Channel #30 configuration 0x00 23.3.2.1/23-4 0x001F CHCONFIG31—Channel #31 configuration 0x00 23.3.2.1/23-4 23.3.2 Register Descriptions This section lists the DMA_MUX registers in address order and describes the registers and their bit fields.
Page 509 DMA Channel Multiplexer (DMA_MUX) NOTE Setting multiple CHCONFIG registers with the same DMA source value results in unpredictable behavior. Table 23-4. DMA Source Configuration DMA_MUX DMA Request Source Input DMA Source Description Number Channel disabled 0x00 Channel disabled Channel disabled Reserved 0x01 Reserved...
Page 510 DMA Channel Multiplexer (DMA_MUX) Table 23-4. DMA Source Configuration (continued) DMA_MUX DMA Request Source Input DMA Source Description Number SCI_G_COMBTX 0x0E SCI_G.SCISR1[TDRE] || SCI_G combined DMA request of the transmit SCI_G.SCISR1[TC] || data register empty, transmit complete, and LIN SCI_G.LINSTAT1[TXRDY] transmit data ready DMA requests SCI_G_COMBRX 0x0F...
Page 511 DMA Channel Multiplexer (DMA_MUX) Table 23-4. DMA Source Configuration (continued) DMA_MUX DMA Request Source Input DMA Source Description Number eMIOS200_FLAG_F15 0x29 eMIOS200.eMIOS200FLAG[F15] eMIOS200 channel 15 flag C_A_TX 0x2A C_A.TX_REQ C_A transmit C_A_RX 0x2B C_A.RX_REQ C_A receive C_B_TX 0x2C C_B.TX_REQ C_B transmit C_B_RX 0x2D C_B.RX_REQ...
Page 512 DMA Channel Multiplexer (DMA_MUX) Table 23-4. DMA Source Configuration (continued) DMA_MUX DMA Request Source Input DMA Source Description Number Always enabled 0x3E Always enabled Always enabled Always enabled 0x3F Always enabled Always enabled Configuring a DMA channel to select source 0 or any of the reserved sources will disable that DMA channel. 23.4 Functional Description The primary purpose of the DMA_MUX is to provide flexibility in the system’s use of the available DMA...
Page 513 DMA Channel Multiplexer (DMA_MUX) PIT Trigger #n+1 Always Disabled Source #0 Peripheral Source #1 Peripheral Source #2 Peripheral Source #3 DMA Channel #n n = 0 to 7 CHCONFIGn[TRIG] Peripheral Source #55 Always Enabled Source #60 Always Enabled Source #63 CHCONFIGn[SOURCE] Figure 23-3.
Page 514 DMA Channel Multiplexer (DMA_MUX) Peripheral Request Trigger DMA Request Figure 23-5. DMA_MUX Channel Triggering: Ignored Trigger This triggering capability may be used with any peripheral that supports DMA transfers and is most useful for two types of situations: • Periodically polling external devices on a particular bus. As an example, the transmit side of an SPI is assigned to a DMA channel with a trigger, as described above.
Page 515 DMA Channel Multiplexer (DMA_MUX) Always Disabled Source #0 Peripheral Source #1 Peripheral Source #2 Peripheral Source #3 DMA Channel #n n = 8 to 31 Peripheral Source #55 Always Enabled Source #60 Always Enabled Source #63 CHCONFIGn[SOURCE] Figure 23-6. DMA_MUX Channel 8–31 Block Diagram 23.4.3 Always Enabled DMA Sources In addition to the 55 peripherals that can be used as DMA sources, there are four additional DMA sources...
Page 516 DMA Channel Multiplexer (DMA_MUX) executions of the minor loop require a new start event be sent. This can either be a new software activation or a transfer request from the DMA channel mux. The options for doing this are: • Transfer all data in a single minor loop.
Page 517 DMA Channel Multiplexer (DMA_MUX) The following code example illustrates steps #1 and #4 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFFFDC000 /* Base addr for PXN20 */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);...
Page 518 DMA Channel Multiplexer (DMA_MUX) 4. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG register, ensuring that the ENBL is set and the TRIG bit is cleared. Example 23-2. Configure DSPI_B Transmit for use with DMA Channel 2, with no periodic triggering capability.
Page 519 DMA Channel Multiplexer (DMA_MUX) 23.5.2.3 Disabling a Source A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCONFIG registers. Some module specific configuration may also be necessary. Refer to the appropriate section for more details. 23.5.2.4 Switching the Source of a DMA Channel 1.
Page 520 DMA Channel Multiplexer (DMA_MUX) volatile unsigned char *CHCONFIG28= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x001C); volatile unsigned char *CHCONFIG29= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x001D); volatile unsigned char *CHCONFIG30= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x001E); volatile unsigned char *CHCONFIG31= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x001F); In File main.c: #include “registers.h”...
Page 521 Chapter 24 Enhanced Direct Memory Access Controller (eDMA) 24.1 Introduction The enhanced direct memory access controller (eDMA) is a second-generation platform block capable of performing complex data movements through 32 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture includes a DMA engine that performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.
Page 522 Enhanced Direct Memory Access Controller (eDMA) 24.1.2 Features The eDMA has these major features: • All data movement via dual-address transfers: read from source, write to destination — Programmable source, destination addresses, transfer size, and support for enhanced addressing modes •...
Page 523 Enhanced Direct Memory Access Controller (eDMA) 24.1.3.2 Debug Mode In debug mode, the eDMA does not accept new transfer requests when its debug input signal is asserted. If the signal is asserted during transfer of a block of data described by a minor loop in the current active channel’s TCD, the eDMA continues operation until completion of the minor loop.
Page 524 Enhanced Direct Memory Access Controller (eDMA) Table 24-1. eDMA Memory Map (continued) Offset from EDMA_BASE Register Access Reset Value Section/Page Size (0xFFF4_4000) 0x001D EDMA_CER—eDMA clear error register 0x00 24.3.2.10/24-18 0x001E EDMA_SSBR—eDMA set start bit register 0x00 24.3.2.11/24-18 0x001F EDMA_CDSBR—eDMA clear done status bit register 0x00 24.3.2.12/24-19 0x0020...
Page 525 Enhanced Direct Memory Access Controller (eDMA) Table 24-1. eDMA Memory Map (continued) Offset from EDMA_BASE Register Access Reset Value Section/Page Size (0xFFF4_4000) 0x0114 EDMA_CPR20—eDMA channel 20 priority register 0x14 24.3.2.16/24-22 0x0115 EDMA_CPR21—eDMA channel 21 priority register 0x15 24.3.2.16/24-22 0x0116 EDMA_CPR22—eDMA channel 22 priority register 0x16 24.3.2.16/24-22 0x0117...
Page 526 Enhanced Direct Memory Access Controller (eDMA) Table 24-1. eDMA Memory Map (continued) Offset from EDMA_BASE Register Access Reset Value Section/Page Size (0xFFF4_4000) 0x1240 TCD18—eDMA transfer control descriptor 18 — 24.3.2.17/24-23 0x1260 TCD19—eDMA transfer control descriptor 19 — 24.3.2.17/24-23 0x1280 TCD20—eDMA transfer control descriptor 20 —...
Page 527 Enhanced Direct Memory Access Controller (eDMA) Table 24-2. eDMA 32-bit Memory Map—Graphical View (continued) Address Register 0xFFF4_4024 eDMA Interrupt Request eDMA Interrupt Request (EDMA_IRQRL, channels 31–16) (EDMA_IRQRL, Channels 15–00) 0xFFF4_4028 Reserved 0xFFF4_402C eDMA Error eDMA Error (EDMA_ERL, channels 31–16) (EDMA_ERL, Channels 15–00) 0xFFF4_4030 Reserved 0xFFF4_4034...
Page 528 Enhanced Direct Memory Access Controller (eDMA) 24.3.2.1 eDMA Control Register (EDMA_CR) The 32-bit EDMA_CR defines the basic operating configuration of the eDMA. Arbitration among the channels can be configured to use a fixed priority or a round robin. In fixed-priority arbitration, the highest priority channel requesting service is selected to execute.
Page 529 Enhanced Direct Memory Access Controller (eDMA) Table 24-3. EDMA_CR Field Descriptions Field Description CXFR Cancel Transfer. 0 Normal operation. 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to be finished. The cancel takes effect after the last write of the current read/write sequence. The CXFR bit clears itself after the cancel has been honored.
Page 530 Enhanced Direct Memory Access Controller (eDMA) 24.3.2.2 eDMA Error Status Register (EDMA_ESR) The EDMA_ESR provides information about the last recorded channel error. Channel errors can be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority register setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle.
Page 531 Enhanced Direct Memory Access Controller (eDMA) The occurrence of any type of error causes the DMA engine to stop the active channel and the appropriate channel bit in the eDMA error register to be asserted. At the same time, the details of the error condition are loaded into the EDMA_ESR.
Page 532 Enhanced Direct Memory Access Controller (eDMA) Table 24-4. EDMA_ESR Field Descriptions (continued) Field Description Source Address Error. 0 No source address configuration error. 1 The last recorded error was a configuration error detected in the TCD.SADDR field, indicating TCD.SADDR is inconsistent with TCD.SSIZE. Source Offset Error.
Page 533 Enhanced Direct Memory Access Controller (eDMA) Both the eDMA request input signal and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the eDMA enable request flag does not effect a channel service request made through software or a linked channel request.
Page 534 Enhanced Direct Memory Access Controller (eDMA) Offset: EDMA_BASE + 0x0014 Access: User read/write EEI31 EEI30 EEI29 EEI28 EEI27 EEI26 EEI25 EEI24 EEI23 EEI22 EEI21 EEI20 EEI19 EEI18 EEI17 EEI16 Reset EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00 Reset Figure 24-5.
Page 535 Enhanced Direct Memory Access Controller (eDMA) Table 24-7. EDMA_SERQR Field Descriptions Field Descriptions No operation. 0 Normal operation. 1 No operation, ignore bits 1–7. SERQ[0:6] Set Enable Request. 0–31 Set corresponding bit in EDMA_ERQRL. 32–63 Reserved. 64–127 Set all bits in EDMA_ERQRL. Note: Bits 2 and 3(SERQR[1:2]) are not used.
Page 536 Enhanced Direct Memory Access Controller (eDMA) bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEI[0]) provides a global set function, forcing the entire contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes. If bit 0 is set, the SEEI command is ignored. This allows multiple byte registers to be written as a 32-bit word.
Page 537 Enhanced Direct Memory Access Controller (eDMA) Table 24-10. EDMA_CEEIR Field Descriptions Field Description No operation. 0 Normal operation. 1 No operation, ignore bits 1–7. CEEI[0:6] Clear Enable Error Interrupt. 0–31 Clear corresponding bit in EDMA_EEIRL. 32–63 Reserved. 64–127 Clear all bits in EDMA_EEIRL. Note: Bits 2 and 3 (CEEIR[1:2]) are not used.
Page 538 Enhanced Direct Memory Access Controller (eDMA) 24.3.2.10 eDMA Clear Error Register (EDMA_CER) The EDMA_CER provides a memory-mapped mechanism to clear a given bit in the EDMA_ERL to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the EDMA_ERL to be cleared.
Page 539 Enhanced Direct Memory Access Controller (eDMA) Table 24-13. EDMA_SSBR Field Descriptions Field Description No operation. 0 Normal operation. 1 No operation, ignore bits 1–7. SSB[0:6] Set START Bit (channel service request). 0–31 Set the corresponding channel’s TCD START bit. 32–63 Reserved.
Page 540 Enhanced Direct Memory Access Controller (eDMA) The DMA engine signals the occurrence of a programmed interrupt on the completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of this register are directly routed to the interrupt controller (INTC).
Page 541 Enhanced Direct Memory Access Controller (eDMA) The contents of this register can also be polled and a non-zero value indicates the presence of a channel error, regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in this register and it provides a single bit indication of any errors.
Page 542 Enhanced Direct Memory Access Controller (eDMA) Address: EDMA_BASE + 0x0034 Access: User read/write R HRS Reset R HRS Reset Figure 24-16. EDMA Hardware Request Status Register Low (EDMA_HRSL) 24.3.2.16 eDMA Channel n Priority Registers (EDMA_CPRn) Table 24-17. EDMA_HRSL Field Descriptions Field Description HRSn...
Page 543 Enhanced Direct Memory Access Controller (eDMA) A channel’s ability to preempt another channel can be disabled by setting EDMA_CPR[DPA]. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority channel’s data transfer; regardless of the lower priority channel’s ECP setting. This allows for a pool of low priority, large data moving channels to be defined.
Page 544 Enhanced Direct Memory Access Controller (eDMA) Table 24-19. TCDn 32-bit Memory Structure (continued) eDMA Offset TCDn Field 0x1000+(32 x n)+0x000C Last source address adjustment (slast) 0x1000+(32 x n)+0x0010 Destination address (daddr) 0x1000+(32 x n)+0x0014 Current major iteration count (citer) Signed destination address offset (doff) 0x1000 (32 x n) 0x0018 Last destination address adjustment / scatter-gather address (dlast_sga) 0x1000+(32 x n)+0x001c...
Page 545 Enhanced Direct Memory Access Controller (eDMA) Table 24-20. TCDn Field Descriptions Bits / Word Offset Name Description [n:n] 0–31 / SADDR Source address. Memory address pointing to the source data. 0x0 [0:31] [0:31] Word 0x0, bits 0–31. 32–36 / SMOD Source address modulo.
Page 546 Enhanced Direct Memory Access Controller (eDMA) Table 24-20. TCDn Field Descriptions (continued) Bits / Word Offset Name Description [n:n] 66–85 MLOFF or Inner “minor” byte transfer count or Minor loop offset 0x8 [2-21] NBYTES If both SMLOE and DMLOE are cleared, this field is part of the byte transfer count. [0:19] If either SMLOE or DMLOE are set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop is...
Page 547 Enhanced Direct Memory Access Controller (eDMA) Table 24-20. TCDn Field Descriptions (continued) Bits / Word Offset Name Description [n:n] 167–175 / CITER Current major iteration count. This 9 or 15-bit count represents the current major loop 0x14 [7:15] [6:14] count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory.
Page 548 Enhanced Direct Memory Access Controller (eDMA) Table 24-20. TCDn Field Descriptions (continued) Bits / Word Offset Name Description [n:n] 225–230 / BITER Starting major iteration count or link channel number. 0x1C [1:6] [0:5] If channel-to-channel linking is disabled (TCD.BITER.E_LINK = 0), then •...
Page 549 Enhanced Direct Memory Access Controller (eDMA) Table 24-20. TCDn Field Descriptions (continued) Bits / Word Offset Name Description [n:n] 250 / MAJOR.E_LINK Enable channel-to-channel linking on major loop completion. As the channel completes 0x1C [26] the outer major loop, this flag enables the linking to another channel, defined by MAJOR.LINKCH[0:5].
Page 550 Enhanced Direct Memory Access Controller (eDMA) The eDMA module is partitioned into two major modules: the DMA engine and the transfer control descriptor local memory. The DMA engine is further partitioned into four submodules, which are detailed below. • DMA engine —...
Page 551 Enhanced Direct Memory Access Controller (eDMA) Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR, BWC, ACTIVE, AND START. Major loop TCD variables are DLAST, SLAST, CITER, BITER, DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF. For descriptors where the sizes are not equal, multiple access of the smaller size data are required for each reference of the larger size.
Page 552 Enhanced Direct Memory Access Controller (eDMA) eDMA SRAM Transfer control descriptor (TCD) Slave write address Slave write data SRAM TCD0 TCDn-1* eDMA engine Bus read data Program model/ channel arbitration Address Control Data path path Slave read data Bus write data Bus address *n = 32 channels eDMA interrupt request...
Page 553 Enhanced Direct Memory Access Controller (eDMA) eDMA SRAM Transfer control descriptor (TCD) Slave write address Slave write data SRAM TCD0 TCDn-1* eDMA engine Bus read data Program model/ channel arbitration Address Control Data path path Slave read data Bus write data Bus address *n = 32 channels eDMA peripheral...
Page 554 Enhanced Direct Memory Access Controller (eDMA) eDMA SRAM Transfer control descriptor (TCD) Slave write address Slave write data SRAM TCD0 TCDn-1* eDMA engine Bus read data Program model/ channel arbitration Address Control Data path path Slave read data Bus write data Bus address *n = 32 channels eDMA peripheral...
Page 555 Enhanced Direct Memory Access Controller (eDMA) transfer control parameter shown in Table 24-21, for the selected channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the system bus unless a configuration error is detected.
Page 556 Enhanced Direct Memory Access Controller (eDMA) Current major loop Example memory array iteration count (CITER) DMA request • Minor loop • • DMA request • Minor loop Major loop • • DMA request • Minor loop • • Figure 24-22. Example of Multiple Loop Iterations Figure 24-23 lists the memory array terms and how the TCD settings interrelate.
Page 557 Enhanced Direct Memory Access Controller (eDMA) Channel-priority errors are identified within a group after that group has been selected as the active group. For the example, all of the channel priorities in group 1 are unique, but some of the channel priorities in group 0 are the same: 1.
Page 558 Enhanced Direct Memory Access Controller (eDMA) Table 24-22. DMA Request Summary for eDMA (continued) DMA Request Channel Source Description DMA_MUX_CHCONFIG9_SOURCE DMA_MUX.CHCONFIG9[SOURCE] DMA MUX channel 9 source DMA_MUX_CHCONFIG10_SOURCE DMA_MUX.CHCONFIG10[SOURCE] DMA MUX channel 10 source DMA_MUX_CHCONFIG11_SOURCE DMA_MUX.CHCONFIG11[SOURCE] DMA MUX channel 11 source DMA_MUX_CHCONFIG12_SOURCE DMA_MUX.CHCONFIG12[SOURCE] DMA MUX channel 12 source...
Page 559 Enhanced Direct Memory Access Controller (eDMA) 24.5.4.2 Round-Robin Group Arbitration, Fixed-Channel Arbitration When one or more DMA requests arrive from one or more groups, the channel with the highest priority from a specific group is serviced first. Groups are serviced starting with the highest group number with a service request and rotating through to the lowest group number containing a service request.
Page 560 Enhanced Direct Memory Access Controller (eDMA) 24.5.5 DMA Transfer 24.5.5.1 Single Request To perform a simple transfer of n bytes of data with one activation, set the major loop to 1 (TCD.CITER = TCD.BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute.
Page 561 Enhanced Direct Memory Access Controller (eDMA) g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word(0x200c)  last iteration of the minor loop  major loop complete 6. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 1 (TCD.BITER). 7. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1. 8.
Page 562 Enhanced Direct Memory Access Controller (eDMA) e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b) f) write_word(0x2008)  third iteration of the minor loop g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word(0x200c)  last iteration of the minor loop 6. eDMA engine writes: TCD.SADDR = 0x1010, TCD.DADDR = 0x2010, TCD.CITER = 1. 7.
Page 563 Enhanced Direct Memory Access Controller (eDMA) Table 24-23. Modulo Feature Example Transfer Address Number 0x12345670 0x12345674 0x12345678 0x1234567C 0x12345670 0x12345674 24.5.6 TCD Status 24.5.6.1 Minor Loop Complete There are two methods to test for minor loop completion when using software initiated service requests. The first method is to read the TCD.CITER field and test for a change.
Page 564 Enhanced Direct Memory Access Controller (eDMA) The TCD.START bit is cleared automatically when the channel begins execution, regardless of how the channel was activated. 24.5.6.2 Active Channel TCD Reads The eDMA will read back the true TCD.SADDR, TCD.DADDR, and TCD.NBYTES values if read while a channel is executing.
Page 565 Enhanced Direct Memory Access Controller (eDMA) 3. Minor loop done  set channel 12 TCD.START bit 4. Minor loop done, major loop done  set channel 7 TCD.START bit When minor loop linking is enabled (TCD.CITER.E_LINK = 1), the TCD.CITER field uses a nine bit vector to form the current iteration count.
Page 566 Enhanced Direct Memory Access Controller (eDMA) The following coherency model is recommended when executing a dynamic channel link or dynamic scatter-gather request: 1. Set the TCD.MAJOR.E_LINK bit. 2. Read back the TCD.MAJOR.E_LINK bit 3. Test the TCD.MAJOR.E_LINK request status: a) If the bit is set, the dynamic link attempt was successful. b) If the bit is cleared, the attempted dynamic link did not succeed, the channel was already retiring.
Page 567 Chapter 25 Fast Ethernet Controller (FEC) 25.1 Introduction This fast ethernet control chapter of the device Reference Manual provides a feature-set overview, a functional block diagram, and transceiver connection information for both the 10 and 100 Mbps MII (media independent interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included.
Page 568 Fast Ethernet Controller (FEC) PBRIDGE_B System Bus Crossbar Switch (XBAR) FEC Block Slave Interface Controller FIFO Controller Descriptor Controller RAM I/F (RISC + microcode) FEC Bus Transmit Receive Counters MDEN FEC_TX_EN FEC_TX_CLK FEC_RX_CLK FEC_TXD[3:0] FEC_RX_DV FEC_CRS FEC_TX_ER FEC_RXD[3:0] FEC_COL FEC_RX_ER MII/7-WIRE DATA FEC_MDIO FEC_MDC...
Page 569 Fast Ethernet Controller (FEC) • Initialization (those internal registers not initialized by the user or hardware) • High level control of the DMA channels (initiating DMA transfers) • Interpreting buffer descriptors • Address recognition for receive frames • Random number generation for transmit collision backoff timer NOTE DMA references in this section refer to the FEC’s DMA engine.
Page 570 Fast Ethernet Controller (FEC) 25.1.3 Features The FEC incorporates the following features: • Support for three different Ethernet physical interfaces: — 100-Mbps IEEE 802.3 MII — 10-Mbps IEEE802.3 MII — 10-Mbps 7-wire interface (industry standard) • Built-in FIFO and DMA controller •...
Page 571 Fast Ethernet Controller (FEC) Throughputs of 200 Mbps in full duplex operations and 100 Mbps in half-duplex operations can be attained. 25.2.2 Interface Options The following interface options are supported. A detailed discussion of the interface configurations is provided in Section 25.4.5, Network Interface Options.
Page 572 Fast Ethernet Controller (FEC) 25.3.1 Top Level Module Memory Map The FEC implementation requires a 1 KB memory map space. This is divided into two sections of 512 bytes each. The first is used for control/status registers. The second contains event/statistic counters held in the MIB block.
Page 573 Fast Ethernet Controller (FEC) Table 25-2. FEC Register Memory Map (continued) Offset from FEC_BASE Register Access Reset Value Section/Page (0xFFF4_C000) 0x0028–0x003F Reserved 0x0040 MMFR—MII Management Frame Register 25.3.4.7/25-15 0x0044 MSCR—MII Speed Control Register 0x0000_0000 25.3.4.8/25-16 0x0048–0x0063 Reserved 0x0064 MIBC—MIB Control/Status Register 0xC000_0000 25.3.4.9/25-18 0x0068–0x0083...
Page 574 Fast Ethernet Controller (FEC) 25.3.3 MIB Block Counters Memory Map Table 25-3 defines the MIB Counters memory map which defines the locations in the MIB RAM space where hardware-maintained counters reside. These fall in the 0xFFF4_C200 – 0xFFF4_C3FF address offset range. The counters are divided into two groups. •...
Page 575 Fast Ethernet Controller (FEC) Table 25-3. MIB Counters Memory Map (continued) Offset from FEC_BASE Mnemonic Description (0xFFF4_C000) 0x024C IEEE_T_FRAME_OK Frames Transmitted OK 0x0250 IEEE_T_1COL Frames Transmitted with Single Collision 0x0254 IEEE_T_MCOL Frames Transmitted with Multiple Collisions 0x0258 IEEE_T_DEF Frames Transmitted after Deferral Delay 0x025C IEEE_T_LCOL Frames Transmitted with Late Collision...
Page 576 Fast Ethernet Controller (FEC) Table 25-3. MIB Counters Memory Map (continued) Offset from FEC_BASE Mnemonic Description (0xFFF4_C000) 0x02D0 IEEE_R_CRC Frames Received with CRC Error 0x02D4 IEEE_R_ALIGN Frames Received with Alignment Error 0x02D8 IEEE_R_MACERR Receive Fifo Overflow count 0x02DC IEEE_R_FDXFC Flow Control Pause frames received 0x02E0 IEEE_R_OCTETS_OK Octet count for Frames Rcvd w/o Error...
Page 577 Fast Ethernet Controller (FEC) • LATE_COL – IEEE_T_LCOL • COL_RETRY_LIM – IEEE_T_EXCOL • XFIFO_UN – IEEET_MACERR Offset: FEC_BASE + 0x0004 Access: User read/write BABR BABT GRA W w1c Reset Reset Figure 25-2. Ethernet Interrupt Event Register (EIR) “w1c” signifies the bit is cleared by writing 1 to it. Table 25-4.
Page 578 Fast Ethernet Controller (FEC) Table 25-4. EIR Field Descriptions (continued) Field Description Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in half duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded. Collision retry limit.
Page 579 Fast Ethernet Controller (FEC) (provided ECR[ETHER_EN] is also set). Once the FEC polls a receive descriptor whose empty bit is not set, the FEC clears R_DES_ACTIVE and ceases receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors have been placed into the receive descriptor ring. The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared.
Page 580 Fast Ethernet Controller (FEC) Offset: FEC_BASE + 0x0014 Access: User read/write X_DES_ACTIVE Reset Reset Figure 25-5. Transmit Descriptor Active Register (TDAR) Table 25-7. TDAR Field Descriptions Field Description 0–6 Reserved, should be cleared. X_DES_ACTIVE Set to one when this register is written, regardless of the value written. Cleared by the FEC device whenever no additional “ready”...
Page 581 Fast Ethernet Controller (FEC) Table 25-8. ECR Field Descriptions Bits Description ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any currently transmitted frame.
Page 582 Fast Ethernet Controller (FEC) Table 25-9. MMFR Field Descriptions Field Description Start of frame delimiter. These bits must be programmed to 01 for a valid MII management frame. Operation code. This field must be programmed to 10 (read) or 01 (write) to generate a valid MII management frame.
Page 583 Fast Ethernet Controller (FEC) Offset: FEC_BASE + 0x0044 Access: User read/write Reset DIS_ PREA MII_SPEED MBLE Reset Figure 25-8. MII Speed Control Register (MSCR) Table 25-10. MSCR Field Descriptions Field Description 0–23 Reserved, should be cleared. DIS_PREAMBLE Asserting this bit causes preamble (32 1’s) not to be prepended to the MII management frame. The MII standard allows the preamble to be dropped if the attached PHY devices does not require it.
Page 584 Fast Ethernet Controller (FEC) Note: Observe maximum system clock frequency when programming MII_SPEED. 25.3.4.9 MIB Control Register (MIBC) The MIBC is a read/write register used to provide control of and to observe the state of the MIB block. This register is accessed by user software if there is a need to disable the MIB block operation. For example, in order to clear all MIB counters in RAM the user should disable the MIB block, then clear all the MIB RAM locations, then enable the MIB block.
Page 585 Fast Ethernet Controller (FEC) should be written only when ECR[ETHER_EN] = 0 (initialization time). Offset: FEC_BASE + 0x0084 Access: User read/write MAX_FL Reset MII_ PROM DRT LOOP MODE Reset Figure 25-10. Receive Control Register (RCR) Table 25-13. RCR Field Descriptions Field Description 0–4...
Page 586 Fast Ethernet Controller (FEC) 25.3.4.11 Transmit Control Register (TCR) The TCR is read/write and is written by the user to configure the transmit block. This register is cleared at system reset. Bits 29 and 30 should be modified only when ECR[ETHER_EN] = 0. Offset: FEC_BASE + 0x00C4 Access: User read/write Reset...
Page 587 Fast Ethernet Controller (FEC) 25.3.4.12 Physical Address Low Register (PALR) The PALR is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit MAC address used in the address recognition process to compare with the DA (destination address) field of receive frames with an individual DA.
Page 588 Fast Ethernet Controller (FEC) Offset: FEC_BASE + 0x00E8 Access: User read/write PADDR2 Reset TYPE Reset Figure 25-13. Physical Address Upper Register (PAUR) Table 25-16. PAUR Field Descriptions Field Description PADDR2 Bytes 4 (bits 0:7) and 5 (bits 8:15) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames.
Page 589 Fast Ethernet Controller (FEC) Table 25-17. OPD Field Descriptions Field Description OPCODE Opcode field used in PAUSE frames. These bits are a constant, 0x0001. PAUSE_DUR Pause duration field used in PAUSE frames. 25.3.4.15 Descriptor Individual Upper Address Register (IAUR) The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual address hash table used in the address recognition process to check for possible match with the DA field of receive frames with an individual DA.
Page 590 Fast Ethernet Controller (FEC) Offset: FEC_BASE + 0x011C Access: User read/write IADDR2 Reset IADDR2 Reset Figure 25-17. Descriptor Individual Lower Address (IALR) Table 25-19. IALR Field Descriptions Field Description IADDR2 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address.
Page 591 Fast Ethernet Controller (FEC) Table 25-20. GAUR Field Descriptions Field Description GADDR1 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
Page 592 Fast Ethernet Controller (FEC) Offset: FEC_BASE + 0x0144 Access: User read/write Reset X_WMRK Reset Figure 25-20. FIFO Transmit FIFO Watermark Register (TFWR) Table 25-22. TFWR Field Descriptions Field Descriptions 0–29 Reserved, should be cleared. X_WMRK Number of bytes written to transmit FIFO before transmission of a frame begins 0x 64 bytes written 10 128 bytes written 11 192 bytes written...
Page 593 Fast Ethernet Controller (FEC) Table 25-23. FRBR Field Descriptions Field Descriptions 0–21 Reserved, read as 0 (except bit 21, which is read as 1). R_BOUND Read-only. Highest valid FIFO RAM address. 30–31 Reserved, should be cleared. 25.3.4.21 FIFO Receive Start Register (FRSR) The FRSR is a 32-bit register with one 8-bit field programmed by the user to indicate the starting address of the receive FIFO.
Page 594 Fast Ethernet Controller (FEC) Offset: FEC_BASE + 0x0180 Access: User read/write R_DES_START Reset R_DES_START Reset Figure 25-23. Receive Descriptor Ring Start Register (ERDSR) Table 25-25. ERDSR Field Descriptions Field Descriptions R_DES_START Pointer to start of receive buffer descriptor queue. 30–31 Reserved, should be cleared.
Page 595 Fast Ethernet Controller (FEC) Table 25-26. ETDSR Field Descriptions Field Descriptions X_DES_START Pointer to start of transmit buffer descriptor queue. 30–31 Reserved, should be cleared. 25.3.4.24 Receive Buffer Size Register (EMRBR) The EMRBR is a 32-bit register with one 7-bit field programmed by the user. The EMRBR register dictates the maximum size of all receive buffers.
Page 596 Fast Ethernet Controller (FEC) 25.4.1 Initialization Sequence This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC, and what locations the user must initialize prior to enabling the FEC. 25.4.1.1 Hardware Controlled Initialization In the FEC, registers and control logic that generate interrupts are reset by hardware.
Page 597 Fast Ethernet Controller (FEC) Table 25-30. FEC User Initialization (Before ECR[ETHER_EN]) Description Initialize FRSR (optional) Initialize EMRBR Initialize ERDSR Initialize ETDSR Initialize (Empty) Transmit Descriptor ring Initialize (Empty) Receive Descriptor ring 25.4.3 Microcontroller Initialization In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted. After the microcontroller initialization sequence is complete, the hardware is ready for operation.
Page 598 Fast Ethernet Controller (FEC) Table 25-32. MII Mode Signal Description EMAC Signal Transmit Clock FEC_TX_CLK Transmit Enable FEC_TX_EN Transmit Data FEC_TXD[3:0] Transmit Error FEC_TX_ER Collision FEC_COL Carrier Sense FEC_CRS Receive Clock FEC_RX_CLK Receive Data Valid FEC_RX_DV Receive Data FEC_RXD[3:0] Receive Error FEC_RX_ER Management Data Clock FEC_MDC...
Page 599 Fast Ethernet Controller (FEC) is busy (FEC_CRS asserts). Before transmitting, the controller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. If so, the transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See Section 25.4.14.1, Transmission Errors, for more details.
Page 600 Fast Ethernet Controller (FEC) • The FEC software driver ensures that the Ready bit cleared in at least one TxBD. • Every frame uses more than one TxBD and every TxBD but the last is written back immediately after the data is fetched. •...
Page 601 Fast Ethernet Controller (FEC) bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory. The Ethernet controller then waits for a new frame. The Ethernet controller receives serial data LSB first. 25.4.8 Ethernet Address Recognition The FEC filters the received frames based on the type of destination address (DA)—individual (unicast),...
Page 602 Fast Ethernet Controller (FEC) Accept/Reject Frame True False Broadcast Addr Receive Address Recognition True False Hash Match BC_REJ = 1 False True Receive Frame Receive Frame Set MC bit in RxBD if multicast Set BC bit in RxBD True Exact Match False True Pause Frame...
Page 603 Fast Ethernet Controller (FEC) Receive Address Recognition Group Individual I/G Address True False True Exact Match False True False Pause Address Hash Search Individual Table Receive Frame Receive Frame Hash Search Group Table True Match True Match Receive Frame False False Reject Frame Receive Frame...
Page 604 Fast Ethernet Controller (FEC) The hash table registers must be initialized by the user. The CRC32 polynomial to use in computing the hash is: X 32 X 26 X 23 X 22 X 16 X 12 X 11 X 10 A table of example Destination Addresses and corresponding hash values is included below for reference.
Page 605 Fast Ethernet Controller (FEC) Table 25-34. Destination Address to 6-Bit Hash (continued) 6-bit Hash (in Hash Decimal 48-bit DA hex) Value C9:ff:ff:ff:ff:ff 0x1B 59:ff:ff:ff:ff:ff 0x1C 79:ff:ff:ff:ff:ff 0x1D 29:ff:ff:ff:ff:ff 0x1E 19:ff:ff:ff:ff:ff 0x1F D1:ff:ff:ff:ff:ff 0x20 F1:ff:ff:ff:ff:ff 0x21 B1:ff:ff:ff:ff:ff 0x22 91:ff:ff:ff:ff:ff 0x23 11:ff:ff:ff:ff:ff 0x24 31:ff:ff:ff:ff:ff 0x25...
Page 606 Fast Ethernet Controller (FEC) Table 25-34. Destination Address to 6-Bit Hash (continued) 6-bit Hash (in Hash Decimal 48-bit DA hex) Value 7D:ff:ff:ff:ff:ff 0x3B FD:ff:ff:ff:ff:ff 0x3C DD:ff:ff:ff:ff:ff 0x3D 9D:ff:ff:ff:ff:ff 0x3E BD:ff:ff:ff:ff:ff 0x3F 25.4.10 Full Duplex Flow Control Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
Page 607 Fast Ethernet Controller (FEC) The user must specify the desired pause duration in the OPD register. Note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit flow control pause (TCR[TFC_PAUSE]) may still be asserted and causes the transmission of a single pause frame.
Page 608 Fast Ethernet Controller (FEC) 25.4.14 Ethernet Error-Handling Procedure The Ethernet controller reports frame reception and transmission error conditions using the FEC RxBDs, the EIR register, and the MIB block counters. 25.4.14.1 Transmission Errors 25.4.14.1.1 Transmitter Underrun If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed.
Page 609 Fast Ethernet Controller (FEC) 25.4.14.2 Reception Errors 25.4.14.2.1 Overrun Error If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV bit in the RxBD. All subsequent data in the frame is discarded. Subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made available.
Page 610 Fast Ethernet Controller (FEC) the data DMA is complete and the buffer descriptor status bits have been written by the DMA engine, the RxBD[E] or TxBD[R] bit is cleared by hardware to signal that the buffer has been “consumed.” Software may poll the BDs to detect when the buffers have been consumed or may rely on the buffer/frame interrupts.
Page 611 Fast Ethernet Controller (FEC) The driver (RxBD software producer) should set up some number of “empty” buffers for the Ethernet by initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive DMA) consumes these buffers by filling them with data as frames are received and clearing the E bit and writing to the L (1 indicates last buffer in frame) bit, the frame status bits (if L = 1), and the length field.
Page 612 Fast Ethernet Controller (FEC) Table 25-36. Receive Buffer Descriptor Field Definitions Halfword Location Field Name Description Offset + 0 Bit 0 Empty. Written by the FEC (=0) and user (=1). 0 The data buffer associated with this BD has been filled with received data, or data reception has been aborted due to an error condition.
Page 613 Fast Ethernet Controller (FEC) Table 25-36. Receive Buffer Descriptor Field Definitions (continued) Halfword Location Field Name Description Offset + 2 Bits [0:15] Data Length Data length. Written by the FEC. Data length is the number of 8-bit data groups (octets) written by the FEC into this BD’s data buffer if L = 0 (the value is equal to EMRBR), or the length of the frame including CRC if L = 1.
Page 614 Fast Ethernet Controller (FEC) Table 25-37. Transmit Buffer Descriptor Field Definitions Halfword Location Field Name Description Offset + 0 Bit 0 Ready. Written by the FEC and the user. 0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer.
Page 615 Chapter 26 FlexRay Communication Controller (FlexRAY) 26.1 Introduction 26.1.1 Reference The following documents are referenced. • FlexRay Communications System Protocol Specification, Version 2.1 Rev A • FlexRay Communications System Electrical Physical Layer Specification, Version 2.1 Rev A 26.1.2 Glossary This section provides a list of terms used in the description of the controller. Table 26-1.
Page 616 FlexRay Communication Controller (FlexRAY) Table 26-1. List of Terms (continued) Term Definition T Microtick Macrotick Media Access Test Symbol Network Idle Time Protocol Engine Protocol Operation Control. Each state of the POC is denoted by POC:state Reception Sequencer Engine Time Control Unit Transmission sync frame null frame or message frame with...
Page 617 FlexRay Communication Controller (FlexRAY) FlexRay FR_A_RX Peripheral FR_A_TX Bridge B config FR_A_TX_EN FR_B_RX SEARCH FR_B_TX FR_B_TX_EN System Memory FR_DBG[0] System Bus FR_DBG[1] BMIF FR_DBG[2] FR_DBG[3] Figure 26-1. FlexRay Block Diagram The protocol engine has two transmitter units TxA and TxB and two receiver units RxA and RxB for sending and receiving frames through the two FlexRay channels.
Page 618 FlexRay Communication Controller (FlexRAY) NOTE The controller does not provide a memory protection scheme for the FlexRay memory. 26.1.5 Features The controller provides the following features: • FlexRay Communications System Protocol Specification, Version 2.1 Rev A compliant protocol implementation • FlexRay Communications System Electrical Physical Layer Specification, Version 2.1 Rev A compliant bus driver interface •...
Page 619 FlexRay Communication Controller (FlexRAY) — As many as 255 entries for each FIFO — Global frame ID filtering, based on both value/mask filters and range filters — Global channel ID filtering — Global message ID filtering for the dynamic segment •...
Page 620 FlexRay Communication Controller (FlexRAY) 26.1.6.2.1 Enter Normal Mode This mode is entered when the application requests the controller to leave the Disabled Mode. If the Normal Mode was entered by leaving the Disabled Mode, the application has to perform the protocol initialization described in Section 26.7.1.2, Protocol Initialization, to achieve full FlexRay functionality.
Page 621 FlexRay Communication Controller (FlexRAY) 26.2.1.3 FR_A_TX_EN — Transmit Enable Channel A The FR_A_TX_EN signal indicates to the FlexRay bus driver that the controller is attempting to transmit data on channel A. 26.2.1.4 FR_B_RX — Receive Data Channel B The FR_B_RX signal carries the receive data for channel B from the corresponding FlexRay bus driver. 26.2.1.5 FR_B_TX —...
Page 622 FlexRay Communication Controller (FlexRAY) To avoid this, • The application should not send the CHI command FREEZE and use the CHI command HALT instead. • Before sending the CHI command FREEZE the application should repeatedly disable all message buffers until all message buffers are disabled.
Page 623 FlexRay Communication Controller (FlexRAY) Table 26-3. FlexRay Memory Map (continued) Offset Register Access 0x0010 Reserved 0x0012 Reserved Interrupt and Error Handling 0x0014 Protocol Operation Control Register (POCR) 0x0016 Global Interrupt Flag and Enable Register (GIFER) 0x0018 Protocol Interrupt Flag Register 0 (PIFR0) 0x001A Protocol Interrupt Flag Register 1 (PIFR1) 0x001C...
Page 624 FlexRay Communication Controller (FlexRAY) Table 26-3. FlexRay Memory Map (continued) Offset Register Access 0x0058 Network Management Vector Length Register (NMVLR) Timer Configuration 0x005A Timer Configuration and Control Register (TICCR) 0x005C Timer 1 Cycle Set Register (TI1CYSR) 0x005E Timer 1 Macrotick Offset Register (TI1MTOR) 0x0060 Timer 2 Configuration Register 0 (TI2CR0) 0x0062...
Page 625 FlexRay Communication Controller (FlexRAY) Table 26-3. FlexRay Memory Map (continued) Offset Register Access 0x0098 Receive FIFO Range Filter Configuration Register (RFRFCFR) 0x009A Receive FIFO Range Filter Control Register (RFRFCTR) Dynamic Segment Status 0x009C Last Dynamic Transmit Slot Channel A Register (LDTXSLAR) 0x009E Last Dynamic Transmit Slot Channel B Register (LDTXSLBR) Protocol Configuration...
Page 626 FlexRay Communication Controller (FlexRAY) Table 26-4. Register Access Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. Reserved bit or field, will not be changed. Application must not write any value different from the reset value. FIELDNAME Identifies the field.
Page 627 FlexRay Communication Controller (FlexRAY) Table 26-6. Register Write Access Restrictions Condition Indication Description Any Time — No write access restriction. Disabled Mode MCR[MEN] = 0 Write access only when the controller is in Disabled Mode. Normal Mode MCR[MEN] = 1 Write access only when the controller is in Normal Mode.
Page 628 FlexRay Communication Controller (FlexRAY) 26.5.2.4 Module Configuration Register (MCR) Base + 0x0002 Write: MEN, SBFF, SCM, CHB, CHA, FUM, FAM, CLKSEL, BITRATE: Disabled Mode SFFE: Disabled Mode or POC:config MEN SBFF SCM CHA SFFE BITRATE Reset Figure 26-3. Module Configuration Register (MCR) This register defines the global configuration of the controller.
Page 629 FlexRay Communication Controller (FlexRAY) Table 26-8. MCR Field Descriptions Field Description CLKSEL Protocol Engine Clock Source Select — This bit is used to select the clock source for the protocol engine. 0 PE clock source is generated by on-chip crystal oscillator. 1 PE clock source is generated by on-chip PLL.
Page 630 FlexRay Communication Controller (FlexRAY) Base + 0x0006 Write: Disabled Mode SMBA[15:4] Reset Figure 26-5. System Memory Base Address Low Register (SYMBADLR) NOTE The system memory base address must be set before the controller is enabled. The system memory base address registers define the base address of the FlexRay memory within the system memory.
Page 631 FlexRay Communication Controller (FlexRAY) Table 26-11. STBSCR Field Descriptions Field Description Write Mode — This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL field only on write access. Strobe Signal Select —...
Page 632 FlexRay Communication Controller (FlexRAY) 26.5.2.7 Message Buffer Data Size Register (MBDSR) Base + 0x000C Write: POC:config MBSEG2DS MBSEG1DS Reset Figure 26-7. Message Buffer Data Size Register (MBDSR) This register defines the size of the message buffer data section for the two message buffer segments in a number of two-byte entities.
Page 633 FlexRay Communication Controller (FlexRAY) Table 26-14. MBSSUTR Field Descriptions Field Description LAST_MB_SEG1 Last Message Buffer In Segment 1 — This field defines the message buffer number of the last individual message buffer that is assigned to the first message buffer segment. The individual message buffers in the first segment correspond to the message buffer control registers MBCCSRn, MBCCFRn, MBFIDRn, MBIDXRn with n <...
Page 634 FlexRay Communication Controller (FlexRAY) Table 26-15. POCR Field Descriptions Field Description ERC_AP External Rate Correction Application — This field is used to trigger application of the external rate correction value defined in the Protocol Configuration Register 21 (PCR21) 00 do not apply external rate correction value 01 reserved 10 Subtract external rate correction value.
Page 635 FlexRay Communication Controller (FlexRAY) This register provides the means to control some of the interrupt request lines and provides the corresponding interrupt flags. The interrupt flags MIF, PRIF, CHIF, RBIF, and TBIF are the outcome of a binary OR of the related individual interrupt flags and interrupt enables. The generation scheme for these flags is depicted in Figure 26-150.
Page 636 FlexRay Communication Controller (FlexRAY) Table 26-16. GIFER Field Descriptions (continued) Field Description RBIF Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive message buffers (MBCCSRn[MTD] = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the corresponding Message Buffer Configuration, Control, Status Registers (MBCCSRn) are asserted.
Page 637 FlexRay Communication Controller (FlexRAY) 26.5.2.11 Protocol Interrupt Flag Register 0 (PIFR0) Base + 0x0018 Write: Normal Mode R FATL INTL ILCF LTXB LTXA TBVB TBVA W w1c Reset Figure 26-11. Protocol Interrupt Flag Register 0 (PIFR0) The register holds one set of the protocol-related individual interrupt flags. Table 26-17.
Page 638 FlexRay Communication Controller (FlexRAY) Table 26-17. PIFR0 Field Descriptions (continued) Field Description CCL_IF Clock Correction Limit Reached Interrupt Flag — This flag is set when the internal calculated offset or rate calculation values have reached or exceeded its configured thresholds as given by the offset_coorection_out field in the Protocol Configuration Register 9 (PCR9) and the rate_correction_out field in the...
Page 639 FlexRay Communication Controller (FlexRAY) 26.5.2.12 Protocol Interrupt Flag Register 1 (PIFR1) Base + 0x001A Write: Normal Mode R EMC PECF SSI3 SSI2 SSI1 SSI0 W w1c Reset Figure 26-12. Protocol Interrupt Flag Register 1 (PIFR1) The register holds one set of the protocol-related individual interrupt flags. Table 26-18.
Page 640 FlexRay Communication Controller (FlexRAY) 26.5.2.13 Protocol Interrupt Enable Register 0 (PIER0) Base + 0x001C Write: Anytime R FATL INTL ILCF LTXB LTXA TBVB TBVA Reset Figure 26-13. Protocol Interrupt Enable Register 0 (PIER0) This register defines whether or not the individual interrupt flags defined in the Protocol Interrupt Flag Register 0 (PIFR0) can generate a protocol interrupt request.
Page 641 FlexRay Communication Controller (FlexRAY) Table 26-19. PIER0 Field Descriptions (continued) Field Description LTXA_IE pLatestTx Violation on Channel A Interrupt Enable — This bit controls LTXA_IF interrupt request generation. 0 interrupt request generation disabled. 1 interrupt request generation enabled. TBVB_IE Transmission across boundary on channel B Interrupt Enable — This bit controls TBVB_IF interrupt request generation.
Page 642 FlexRay Communication Controller (FlexRAY) Table 26-20. PIER1 Field Descriptions (continued) Field Description PECF_IE Protocol Engine Communication Failure Interrupt Enable — This bit controls PECF_IF interrupt request generation. 0 interrupt request generation disabled. 1 interrupt request generation enabled. PSC_IE Protocol State Changed Interrupt Enable — This bit controls PSC_IF interrupt request generation. 0 interrupt request generation disabled.
Page 643 FlexRay Communication Controller (FlexRAY) Table 26-21. CHIERFR Field Descriptions (continued) Field Description PCMI_EF Protocol Command Ignored Error Flag — This flag is set if the application has issued a POC command by writing to the POCCMD field in the Protocol Operation Control Register (POCR) while the BSY flag is equal to 1.
Page 644 FlexRay Communication Controller (FlexRAY) Table 26-21. CHIERFR Field Descriptions (continued) Field Description DPL_EF Dynamic Payload Length Error Flag — This flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the dynamic segment is greater than the maximum payload length for the dynamic segment as it is configured in the corresponding protocol configuration register field max_payload_length_dynamic in the Protocol Configuration Register 24...
Page 645 FlexRay Communication Controller (FlexRAY) Table 26-22. MBIVEC Field Descriptions Field Description TBIVEC Transmit Buffer Interrupt Vector — This field provides the number of the lowest numbered enabled transmit message buffer that has its interrupt status flag MBIF and its interrupt enable bit MBIE set. If there is no transmit message buffer with the interrupt status flag MBIF and the interrupt enable MBIE bits asserted, the value in this field is set to 0.
Page 646 FlexRay Communication Controller (FlexRAY) one error indicator bit is set to 1. The counter wraps around after it has reached the maximum value. For more information on slot status monitoring see Section 26.6.18, Slot Status Monitoring. Table 26-24. CBSERCR Field Descriptions Field Description STATUS_ERR_CNT Channel Status Error Counter —...
Page 647 FlexRay Communication Controller (FlexRAY) Table 26-25. PSR0 Field Descriptions (continued) Field Description STARTUP Startup State — protocol related variable: vPOC!StartupState. This field indicates the current sub-state of the STATE startup procedure. 0000 reserved 0001 reserved 0010 POC:coldstart collision resolution 0011 POC:coldstart listen 0100 POC:integration consistency check...
Page 648 FlexRay Communication Controller (FlexRAY) Table 26-26. PSR1 Field Descriptions (continued) Field Description REMCSAT Remaining Coldstart Attempts — protocol related variable: vRemainingColdstartAttempts This field provides the number of remaining cold start attempts that the controller will execute. Leading Cold Start Path Noise — protocol related variable: vPOC!ColdstartNoise This status bit is set if the controller has reached the POC:normal active...
Page 649 FlexRay Communication Controller (FlexRAY) Table 26-27. PSR2 Field Descriptions Field Description NBVB NIT Boundary Violation on Channel B — protocol related variable: vSS!BViolation for NIT on channel B. This status bit is set when there was some media activity on the FlexRay bus channel B at the end of the NIT. 0 No such event.
Page 650 FlexRay Communication Controller (FlexRAY) Table 26-27. PSR2 Field Descriptions (continued) Field Description SSEA Symbol Window Syntax Error on Channel A — protocol related variable: vSS!SyntaxError for symbol window on channel A. This status bit is set when a syntax error was detected during the symbol window on channel A. 0 No such event.
Page 651 FlexRay Communication Controller (FlexRAY) Table 26-28. PSR3 Field Descriptions (continued) Field Description ACEB Aggregated Content Error on Channel B — This flag is set when a content error has been detected on channel B. Content errors are detected in the communication slots, the symbol window, and the NIT. 0 No content error detected.
Page 652 FlexRay Communication Controller (FlexRAY) This register provides the macrotick count of the current communication cycle. Table 26-29. MTCTR Field Descriptions Field Description MTCT Macrotick Counter — protocol related variable: vMacrotick This field provides the macrotick count of the current communication cycle. 26.5.2.24 Cycle Counter Register (CYCTR) Base + 0x0032 CYCCNT...
Page 653 FlexRay Communication Controller (FlexRAY) 26.5.2.26 Slot Counter Channel B Register (SLTCTBR) Base + 0x0036 SLOTCNTB Reset Figure 26-26. Slot Counter Channel B Register (SLTCTBR) This register provides the number of the current slot in the current communication cycle for channel B. Table 26-32.
Page 654 FlexRay Communication Controller (FlexRAY) 26.5.2.28 Offset Correction Value Register (OFCORVR) Base + 0x003A Additional Reset: RUN Command OFFSETCORR Reset Figure 26-28. Offset Correction Value Register (OFCORVR) This register provides the sign extended offset correction value in microticks as it was calculated by the clock synchronization algorithm.
Page 655 FlexRay Communication Controller (FlexRAY) Table 26-35. CIFRR Field Descriptions Field Description Module Interrupt Flag — This flag is set if there is at least one interrupt source that has its interrupt flag asserted. 0 No interrupt source has its interrupt flag asserted. 1 At least one interrupt source has its interrupt flag asserted.
Page 656 FlexRay Communication Controller (FlexRAY) 26.5.2.31 Sync Frame Counter Register (SFCNTR) Base + 0x0040 Additional Reset: RUN Command SFEVB SFEVA SFODB SFODA Reset Figure 26-31. Sync Frame Counter Register (SFCNTR) This register provides the number of synchronization frames that are used for clock synchronization in the last even and in the last odd numbered communication cycle.
Page 657 FlexRay Communication Controller (FlexRAY) Table 26-38. SFTOR Field Description Field Description SFTOR Sync Frame Table Offset — The offset of the Sync Frame Tables in the Flexray Memory. This offset is required to be 16-bit aligned. Thus STF_OFFSET[0] is always 0. 26.5.2.33 Sync Frame Table Configuration, Control, Status Register (SFTCCSR) Base + 0x0044 Write: Normal Mode...
Page 658 FlexRay Communication Controller (FlexRAY) Table 26-39. SFTCCSR Field Descriptions (continued) Field Description One Pair Trigger — This trigger bit controls whether the controller writes continuously or only one pair of Sync Frame Tables into the FlexRay memory. If this trigger is set to 1 while SDVEN or SIDEN is set to 1, the controller writes only one pair of the enabled Sync Frame Tables corresponding to the next even-odd-cycle pair into the FlexRay memory.
Page 659 FlexRay Communication Controller (FlexRAY) 26.5.2.35 Sync Frame ID Acceptance Filter Value Register (SFIDAFVR) Base + 0x0048 Write: POC:config FVAL Reset Figure 26-35. Sync Frame ID Acceptance Filter Value Register (SFIDAFVR) This register defines the sync frame acceptance filter value. For details on filtering, see Section 26.6.15, Sync Frame Filtering.
Page 660 FlexRay Communication Controller (FlexRAY) Each of these six registers holds one part of the Network Management Vector. The length of the Network Management Vector is configured in the Network Management Vector Length Register (NMVLR). If NMVLR is programmed with a value that is less than 12 bytes, the remaining bytes of the Network Management Vector Registers (NMVR0–NMVR5), which are not used for the Network Management...
Page 661 FlexRay Communication Controller (FlexRAY) 26.5.2.39 Timer Configuration and Control Register (TICCR) Base + 0x005A Write: T2_CFG: POC:config T2_REP, T1_REP, T1SP, T2SP, T1TR, T2TR: Normal Mode T2ST T1ST T2SP T2TR T1SP T1TR Reset Figure 26-39. Timer Configuration and Control Register (TICCR) This register is used to configure and control the two timers T1 and T2.
Page 662 FlexRay Communication Controller (FlexRAY) 26.5.2.40 Timer 1 Cycle Set Register (TI1CYSR) Base + 0x005C Write: Anytime T1_CYC_VAL T1_CYC_MSK Reset Figure 26-40. Timer 1 Cycle Set Register (TI1CYSR) This register defines the cycle filter value and the cycle filter mask for timer T1. For a detailed description of timer T1, refer to Section 26.6.17.1, Absolute Timer T1.
Page 663 FlexRay Communication Controller (FlexRAY) 26.5.2.42 Timer 2 Configuration Register 0 (TI2CR0) Base + 0x0060 Write: Anytime T2_CYC_VAL T2_CYC_MSK T2_MTCNT[31:16] Reset Figure 26-42. Timer 2 Configuration Register 0 (TI2CR0) The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control Register (TICCR).
Page 664 FlexRay Communication Controller (FlexRAY) The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control Register (TICCR). For a detailed description of timer T2, refer to Section 26.6.17.2, Absolute / Relative Timer T2. Table 26-50.
Page 665 FlexRay Communication Controller (FlexRAY) Table 26-51. SSSR Field Descriptions (continued) Field Description Selector — This field selects one of the four internal slot status selection registers for access. 00 Select SSSR0. 01 Select SSSR1. 10 Select SSSR2. 11 Select SSSR3. SLOTNUMBER Slot Number —...
Page 666 FlexRay Communication Controller (FlexRAY) Table 26-53. SSCCR Field Descriptions Field Description Write Mode — This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL field only on write access. Selector —...
Page 667 FlexRay Communication Controller (FlexRAY) 26.5.2.46 Slot Status Registers (SSR0–SSR7) Base + 0x0068 (SSR0) Base + 0x006A (SSR1) Base + 0x006C (SSR2) Base + 0x006E (SSR3) Base + 0x0070 (SSR4) Base + 0x0072 (SSR5) Base + 0x0074 (SSR6) Base + 0x0076 (SSR7) R VFB Reset Figure 26-46.
Page 668 FlexRay Communication Controller (FlexRAY) Table 26-55. SSR0–SSR7 Field Descriptions (continued) Field Description Valid Frame on Channel A — protocol related variable: vSS!ValidFrame channel A vSS!ValidFrame = 0. vSS!ValidFrame = 1. Sync Frame Indicator Channel A — protocol related variable: vRF!Header!SyFIndicator channel A vRF!Header!SyFIndicator = 0.
Page 669 FlexRay Communication Controller (FlexRAY) NOTE If the counter has reached its maximum value 0xFFFF and is in the multicycle mode (SSCCRn[MCY] = 1), the counter is not reset to 0x0000. The application can reset the counter by clearing the SSCCRn[MCY] bit and waiting for the next cycle start, when the controller clears the counter.
Page 670 FlexRay Communication Controller (FlexRAY) Table 26-58. MTSBCFR Field Descriptions Field Description Media Access Test Symbol Transmission Enable — This control bit is used to enable and disable the transmission of the Media Access Test Symbol in the selected set of cycles. 0 MTS transmission disabled.
Page 671 FlexRay Communication Controller (FlexRAY) Base + 0x00E8 Write: Disabled Mode SMBA[31:16] Reset Figure 26-51. Receive FIFO System Memory Base Address High Register (RFSYMBADHR) Base + 0x00EA Write: Disabled Mode SMBA[15:4] Reset Figure 26-52. Receive FIFO System Memory Base Address Low Register (RFSYMBADLR) These registers define the system memory base address for the receive FIFO if the FIFO address mode bit MCR[FAM] is set to 1.
Page 672 FlexRay Communication Controller (FlexRAY) 26.5.2.53 Receive FIFO Watermark and Selection Register (RFWMSR) Base + 0x0086 Write: : POC:config, SEL: Anytime Reset Figure 26-54. Receive FIFO Watermark and Selection Register (RFWMSR) This register is used to • select a receiver FIFO for subsequent programming access through the receiver FIFO configuration registers summarized in Table 26-62.
Page 673 FlexRay Communication Controller (FlexRAY) Table 26-64. RFSIR Field Descriptions Field Description SIDX Start Index — This field defines the number of the message buffer header field of the first message buffer of the SIDX selected FIFO. The controller uses the value of the SIDX field to determine the physical location of the receiver FIFO’s first message buffer header field.
Page 674 FlexRay Communication Controller (FlexRAY) NOTE If the FIFO is empty, the RDIDX field points to an physical message buffer with invalid content. 26.5.2.57 Receive FIFO B Read Index Register (RFBRIR) Base + 0x008E RDIDX Reset Figure 26-58. Receive FIFO B Read Index Register (RFBRIR) This register provides the message buffer header index of the next available FIFO B entry that the application can read.
Page 675 FlexRay Communication Controller (FlexRAY) NOTE If the pop count value PCA/PCB is greater than the current FIFO fill level FLB/FLA, than the FIFO is empty after the update. No notification is given that not the required number of entries was removed. 26.5.2.59 Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR) Base + 0x0090...
Page 676 FlexRay Communication Controller (FlexRAY) 26.5.2.61 Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) Base + 0x0094 Write: POC:config FIDRFVAL /FIDRFVAL Reset Figure 26-62. Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) This register defines the filter value for the frame ID rejection filter of the selected FIFO. For details on frame ID filtering see Section 26.6.9.9, FIFO Filtering.
Page 677 FlexRay Communication Controller (FlexRAY) Table 26-73. RFRFCFR Field Descriptions Field Description Write Mode — This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL and IBD field only on write access. Interval Boundary —...
Page 678 FlexRay Communication Controller (FlexRAY) Table 26-74. RFRFCTR Field Descriptions (continued) Field Description F1EN Range Filter 1 Enable — This control bit is used to enable and disable the frame ID range filter 1. 0 Range filter 1 disabled. 1 Range filter 1 enabled. F0EN Range Filter 0 Enable —...
Page 679 FlexRay Communication Controller (FlexRAY) 26.5.2.67 Protocol Configuration Registers The following configuration registers provide the necessary configuration information to the protocol engine. The individual values in the registers are described in Table 26-77. For more details about the FlexRay related configuration parameters and the allowed parameter ranges, see FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
Page 680 FlexRay Communication Controller (FlexRAY) Table 26-77. Protocol Configuration Register Fields (continued) Name Description Unit T cluster_drift_damping pClusterDriftDamping T comp_accepted_startup_range_a pdAcceptedStartupRange pDelayCompensation[A] T comp_accepted_startup_range_b pdAcceptedStartupRange pDelayCompensation[B] T listen_timeout pdListenTimeout 14/15 key_slot_id pKeySlotId number key_slot_used_for_startup pKeySlotUsedForStartup bool key_slot_used_for_sync pKeySlotUsedForSync bool latest_tx gNumberOfMinislots pLatestTx minislot sync_node_max...
Page 681 FlexRay Communication Controller (FlexRAY) 26.5.2.67.1 Protocol Configuration Register 0 (PCR0) Base + 0x00A0 Write: POC:config action_point_offset static_slot_length Reset Figure 26-68. Protocol Configuration Register 0 (PCR0) 26.5.2.67.2 Protocol Configuration Register 1 (PCR1) Base + 0x00A2 Write: POC:config macro_after_first_static_slot Reset Figure 26-69. Protocol Configuration Register 1 (PCR1) 26.5.2.67.3 Protocol Configuration Register 2 (PCR2) Base + 0x00A4 Write:...
Page 682 FlexRay Communication Controller (FlexRAY) 26.5.2.67.6 Protocol Configuration Register 5 (PCR5) Base + 0x00AA Write: POC:config tss_transmitter wakeup_symbol_tx_low wakeup_symbol_rx_idle Reset Figure 26-73. Protocol Configuration Register 5 (PCR5) 26.5.2.67.7 Protocol Configuration Register 6 (PCR6) Base + 0x00AC Write: POC:config symbol_window_after_action_point macro_initial_offset_a Reset Figure 26-74.
Page 683 FlexRay Communication Controller (FlexRAY) 26.5.2.67.11 Protocol Configuration Register 10 (PCR10) Base + 0x00B4 Write: POC:config R single wake _slot macro_per_cycle chan abled Reset Figure 26-78. Protocol Configuration Register 10 (PCR10) 26.5.2.67.12 Protocol Configuration Register 11 (PCR11) Base + 0x00B6 Write: POC:config R key_ key_...
Page 684 FlexRay Communication Controller (FlexRAY) 26.5.2.67.15 Protocol Configuration Register 14 (PCR14) Base + 0x00BC Write: POC:config rate_correction_out listen_timeout[20:16] Reset Figure 26-82. Protocol Configuration Register 14 (PCR14) 26.5.2.67.16 Protocol Configuration Register 15 (PCR15) Base + 0x00BE Write: POC:config listen_timeout[15:0] Reset Figure 26-83. Protocol Configuration Register 15 (PCR15) 26.5.2.67.17 Protocol Configuration Register 16 (PCR16) Base + 0x00C0 Write:...
Page 685 FlexRay Communication Controller (FlexRAY) 26.5.2.67.20 Protocol Configuration Register 19 (PCR19) Base + 0x00C6 Write: POC:config decoding_correction_a payload_length_static Reset Figure 26-87. Protocol Configuration Register 19 (PCR19) 26.5.2.67.21 Protocol Configuration Register 20 (PCR20) Base + 0x00C8 Write: POC:config micro_initial_offset_b micro_initial_offset_a Reset Figure 26-88. Protocol Configuration Register 20 (PCR20) 26.5.2.67.22 Protocol Configuration Register 21 (PCR21) Base + 0x00CA Write:...
Page 686 FlexRay Communication Controller (FlexRAY) 26.5.2.67.25 Protocol Configuration Register 24 (PCR24) Base + 0x00D0 Write: POC:config micro_per_cycle_min cluster_drift_damping max_payload_length_dynamic [19:16] Reset Figure 26-92. Protocol Configuration Register 24 (PCR24) 26.5.2.67.26 Protocol Configuration Register 25 (PCR25) Base + 0x00D2 Write: POC:config micro_per_cycle_min[15:0] Reset Figure 26-93.
Page 687 FlexRay Communication Controller (FlexRAY) 26.5.2.67.30 Protocol Configuration Register 29 (PCR29) Base + 0x00DA Write: POC:config extern_offset_ minislots_max correction Reset Figure 26-97. Protocol Configuration Register 29 (PCR29) 26.5.2.67.31 Protocol Configuration Register 30 (PCR30) Base + 0x00DC Write: POC:config sync_node_max Reset Figure 26-98. Protocol Configuration Register 30 (PCR30) 26.5.2.68 Message Buffer Configuration, Control, Status Registers (MBCCSRn) Base + 0x0100 (MBCCSR0) Write: MCM, MBT, MTD:...
Page 688 FlexRay Communication Controller (FlexRAY) Table 26-79. MBCCSRn Field Descriptions Field Description Message Buffer Configuration Message Buffer Commit Mode — This bit configures the commit mode of a double buffered message buffer. 0 Streaming commit mode. 1 Immediate commit mode. Message Buffer Type — This bit configures the buffering type of a transmit message buffer. 0 Single buffered message buffer.
Page 689 FlexRay Communication Controller (FlexRAY) 26.5.2.69 Message Buffer Cycle Counter Filter Registers (MBCCFRn) Base + 0x0102 (MBCCFR0) Write: POC:config or MB_DIS Base + 0x010A (MBCCFR1) Base + 0x04FA (MBCCFR127) CHB CCFE CCFMSK CCFVAL Reset Figure 26-100. Message Buffer Cycle Counter Filter Registers (MBCCFRn) This register contains message buffer configuration data for the transmission mode, the channel assignment, and for the cycle counter filtering.
Page 690 FlexRay Communication Controller (FlexRAY) NOTE If at least one message buffer assigned to a certain slot is assigned to both channels, then all message buffers assigned to this slot have to be assigned to both channels. Otherwise, the message buffer configuration is illegal and the result of the message buffer search is not defined.
Page 691 FlexRay Communication Controller (FlexRAY) NOTE If a message buffer is assigned to the last slot in a FlexyRay communication cycle and a system memory access timeout or illegal address access occurs during the system memory access in this slot, it is possible that for all future communication required: •...
Page 692 FlexRay Communication Controller (FlexRAY) 26.6 Functional Description This section provides a detailed description of the functionality implemented in the controller. 26.6.1 Message Buffer Concept The controller uses a data structure called message buffer to store frame data, configuration, control, and status data.
Page 693 FlexRay Communication Controller (FlexRAY) Specification, Version 2.1 Rev A. A detailed description of the usage and the content of the frame header is provided in Section 26.6.5.2.1, Frame Header Description. 26.6.2.1.2 Data Field Offset The data field offset follows the frame header in the message buffer data field and occupies two bytes. It contains the offset of the corresponding message buffer data field with respect to the controller FlexRay memory base address as provided by SMBA field in the System Memory Base Address Register...
Page 694 FlexRay Communication Controller (FlexRAY) Each individual message buffer consists of two parts, the physical message buffer, which is located in the FlexRay memory, and the message buffer control data, which are located in dedicated registers. The structure of an individual message buffer is given in Figure 26-104.
Page 695 FlexRay Communication Controller (FlexRAY) 26.6.3.2 Receive Shadow Buffers The receive shadow buffers are required for the frame reception process for individual message buffers. The controller provides four receive shadow buffers, one receive shadow buffer per channel and per message buffer segment. Each receive shadow buffer consists of two parts, the physical message buffer located in the FlexRay memory and the receive shadow buffer control registers located in dedicated registers.
Page 696 FlexRay Communication Controller (FlexRAY) A receive FIFO consists of a set of physical message buffers in the FlexRay memory and a set of receive FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in Figure 26-106.
Page 697 FlexRay Communication Controller (FlexRAY) (min) RFDSR[ENTRY_SIZE] * 2 bytes SADR_MBDF[n] Frame Data[n] SADR_MBDF[i] Frame Data[i] SADR_MBDF[1] Frame Data[1] Message Buffer Data Fields SADR_MBHF[n] Frame Header[n] Data Field Offset[n] Slot Status[n] SADR_MBHF[i] Frame Header[i] Data Field Offset[i] Slot Status[i] SADR_MBHF[1] Frame Header[1] Data Field Offset[1] Slot Status[1] Message Buffer Header Fields...
Page 698 FlexRay Communication Controller (FlexRAY) message buffers and the number of individual message buffers that are used. For more details, see Section 26.6.3.1.1, Individual Message Buffer Segments. Specific Configuration Data The set of message buffer specific configuration data for individual message buffers is located in the following registers.
Page 699 FlexRay Communication Controller (FlexRAY) • Receive FIFO Watermark and Selection Register (RFWMSR) • Receive FIFO Start Index Register (RFSIR) • Receive FIFO Depth and Size Register (RFDSR) • Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR) • Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR) •...
Page 700 FlexRay Communication Controller (FlexRAY) System Memory Sync Frame Table Area Message Buffer Data Area Frame Header Data Field Offset Slot Status Message Buffer Header Fields Receive FIFO B Frame Header Data Field Offset Slot Status Frame Header Data Field Offset Slot Status Message Buffer Header Fields Receive FIFO A...
Page 701 FlexRay Communication Controller (FlexRAY) System Memory FIFO Message Buffer Data Area Frame Header Data Field Offset Slot Status Message Buffer Header Fields Receive FIFO B Frame Header Data Field Offset Slot Status Frame Header Data Field Offset Slot Status Message Buffer Header Fields Receive FIFO A Frame Header Data Field Offset...
Page 702 FlexRay Communication Controller (FlexRAY) SADR_MBHF = (i * 10) + SYMBADR[SMBA]; (0 i < 1024) Eqn. 26-9 < 3. The message buffer header fields for each FIFO have to be a contiguous area. 26.6.4.4 Message Buffer Header Area (MCR[FAM] = 1) The message buffer header area contains all message buffer header fields of the physical message buffers for the individual message buffers and receiver shadow buffers.
Page 703 FlexRay Communication Controller (FlexRAY) 26.6.5.2 Message Buffer Header Field Description This section provides a detailed description of the usage and content of the message buffer header field. A description of the structure of the message buffer header fields is given in Section 26.6.2.1, Message Buffer Header Field.
Page 704 FlexRay Communication Controller (FlexRAY) CYCCNT PLDLEN HDCRC = not used Figure 26-111. Frame Header Structure (Transmit Message Buffer for Key Slot) Frame Header Access The frame header is located in the FlexRay memory. To ensure data consistency, the application must follow the write access scheme described below.
Page 705 FlexRay Communication Controller (FlexRAY) For transmit message buffers assigned to the dynamic segment, the PLDLEN value must be less than or equal to the value of the max_payload_length_dynamic field in the Protocol Configuration Register 24 (PCR24). If this is not fulfilled, the dynamic payload length error flag DPL_EF in the CHI Error Flag Register (CHIERFR) is set when the message buffer is under transmission.
Page 706 FlexRay Communication Controller (FlexRAY) Table 26-86. Frame Header Field Descriptions (Transmit Message Buffer) (continued) Field Description PLDLEN Payload Length — This field is checked and used as described in Frame Header Checks. HDCRC Header CRC — This field provides the value of the Header CRC field for the frame transmitted from the message buffer.
Page 707 FlexRay Communication Controller (FlexRAY) R VFB Reset – – – – – – – – – – – – – – – – Figure 26-112. Receive Message Buffer Slot Status Structure (ChAB) Reset – – – – – – – –...
Page 708 FlexRay Communication Controller (FlexRAY) Table 26-88. Receive Message Buffer Slot Status Field Descriptions (continued) Field Description Sync Frame Indicator Channel A — protocol related variable: vRF!Header!SyFIndicator channel A. vRF!Header!SyFIndicator = 0. vRF!Header!SyFIndicator = 1. Null Frame Indicator Channel A — protocol related variable: vRF!Header!NFIndicator channel A.
Page 709 FlexRay Communication Controller (FlexRAY) Reset – – – – – – – – – – – – – – – – Figure 26-116. Transmit Message Buffer Slot Status Structure (ChA) R VFB Reset – – – – – – – –...
Page 710 FlexRay Communication Controller (FlexRAY) Table 26-90. Transmit Message Buffer Slot Status Structure Field Descriptions (continued) Field Description Syntax Error on Channel A — protocol related variable: vSS!SyntaxError channel A. vSS!SyntaxError = 0. vSS!SyntaxError = 1. Content Error on Channel A — protocol related variable: vSS!ContentError channel A.
Page 711 FlexRay Communication Controller (FlexRAY) 26.6.5.3.1 Message Buffer Data Field Read Access For transmit message buffers, the controller will not modify the content of the Message Buffer Data Field. Thus the application can read back the data at any time without any impact on data consistency. For receive message buffers the application must lock the related receive message buffer and retrieve the message buffer header index from the Message Buffer Index Registers...
Page 712 FlexRay Communication Controller (FlexRAY) Before an individual message buffer can be used, it must be configured by the application. After the initial configuration, the message buffer can be reconfigured later. The set of the configuration data for individual message buffers is given in Section 26.6.3.4.1, Individual Message Buffer Configuration Data.
Page 713 FlexRay Communication Controller (FlexRAY) The message buffer specific configuration data are 1. MCM, MBT, MTD bits in Message Buffer Configuration, Control, Status Registers (MBCCSRn) 2. all fields and bits in Message Buffer Cycle Counter Filter Registers (MBCCFRn) 3. all fields and bits in Message Buffer Frame ID Registers (MBFIDRn) 4.
Page 714 FlexRay Communication Controller (FlexRAY) Message Buffer Header Field: Frame Header Message Buffer Header Field: Data Field Offset MBIDXRn[MBIDX] MBCCSRn[CMT] Message Buffer Data Field: DATA[0-N] Message Buffer Header Field: Slot Status MBCCSRn[MBT/MTD] MBCCFRn[MTM/CHA/CHB/CCF*] MBFIDRn[FID] Figure 26-119. Single Transmit Message Buffer Access Regions Table 26-95.
Page 715 FlexRay Communication Controller (FlexRAY) RESET_STATE HDis Idle CCSu HDisLck CCSa CCTx HLck HLckCCSa CCNf CCMa HLckCCNf HLckCCMa Figure 26-120. Single Transmit Message Buffer States Table 26-96. Single Transmit Message Buffer State Description MBCCSRn Access Region State Description LCKS Appl. Module Idle –...
Page 716 FlexRay Communication Controller (FlexRAY) Table 26-96. Single Transmit Message Buffer State Description (continued) MBCCSRn Access Region State Description LCKS Appl. Module CCSu – Status Update - Message buffer status update. Update of status flags, the slot status field, and the header index. 26.6.6.2.3 Message Buffer Transitions Application Transitions...
Page 717 FlexRay Communication Controller (FlexRAY) Table 26-98. Single Transmit Message Buffer Module Transitions (continued) Transition Condition Description slot match and Message Available - Message buffer is assigned to next slot and cycle counter CycleCounter match filter matches. slot start and Transmission Slot Start - Slot Start and commit bit CMT is set. MBCCSRn[CMT] = 1 In case of a dynamic slot, pLatestTx is not exceeded.
Page 718 FlexRay Communication Controller (FlexRAY) As indicated by Table 26-96, the application shall write to the message buffer data field and change the commit bit CMT only if the transmit message buffer is in one of the states HDis, HDisLck, HLck, HLckCCSa, HLckCCMa, or HLckCCMa.
Page 719 FlexRay Communication Controller (FlexRAY) The amount of message data read from the FlexRay memory and transferred to the FlexRay bus is determined by the following three items 1. the message buffer segment that the message buffer is assigned to, as defined by the Message Buffer Segment Size and Utilization Register (MBSSUTR).
Page 720 FlexRay Communication Controller (FlexRAY) HLck HLckCCSa HLckCCNf HLck search[s+1] null frame transmit slot s slot s+1 slot s+2 Figure 26-124. Null Frame Transmission from HLck state If a transmit message buffer is in the CCSa or HLckCCSa state at the start of the transmission slot, a null frame is transmitted in any case, even if the message buffer is unlocked or committed before the transmission slot starts.
Page 721 FlexRay Communication Controller (FlexRAY) buffer and triggers the status updated transition SU. With the SU transition, the controller sets the message buffer interrupt flag MBCCSRn[MBIF] to indicate the successful message transmission. Depending on the transmission mode flag MBCCFRn[MTM], the controller changes the commit flag MBCCSRn[CMT] and the valid flag MBCCSRn[DVAL].
Page 722 FlexRay Communication Controller (FlexRAY) To certain message buffer fields, both the application and the controller have access. To ensure data consistency, a message buffer locking scheme is implemented that is used to control the access to the data, control, and status bits of a message buffer. The access regions for receive message buffers are depicted in Figure 26-127.
Page 723 FlexRay Communication Controller (FlexRAY) RESET_STATE HDis Idle CCSu HDisLck CCBs CCRx HLck HLckCCBs HLckCCRx Figure 26-128. Receive Message Buffer States Table 26-101. Receive Message Buffer States and Access MBCCSRn Access from State Description LCKS Appl. Module Idle – Idle - Message Buffer is idle. Included in message buffer search.
Page 724 FlexRay Communication Controller (FlexRAY) The enable and disable commands issued by writing 1 to the trigger bit MBCCSRn[EDT]. The transition that will be triggered by each of these command depends on the current value of the status bit MBCCSRn[EDS]. If the command triggers the disable transition HD and the message buffer is in one of the states CCBs, HLckCCBs, or CCRx, the disable transition has no effect (command is ignored) and the message buffer state is not changed.
Page 725 FlexRay Communication Controller (FlexRAY) same time as the application locks the message buffer by the HL transition, the intermediate state is CCRx and the resulting state is locked buffer subscribed state HLckCCRx. Table 26-104. Receive Message Buffer Transition Priorities State Priorities Description module vs.
Page 726 FlexRay Communication Controller (FlexRAY) Table 26-105. Receive Message Buffer Update vSS!ValidFrame vRF!Header!NFIndicator Update description Valid non-null frame received. - Message Buffer Data Field updated. - Frame Header Field updated. - Slot Status Field updated. - DUP:= 1 - DVAL:= 1 - MBIF:= 1 Valid null frame received.
Page 727 FlexRay Communication Controller (FlexRAY) The amount of message data written into the message buffer data field of the receive shadow buffer is determined by the following items: 1. The message buffer segment that the message buffer is assigned to, as defined by the Message Buffer Segment Size and Utilization Register (MBSSUTR).
Page 728 FlexRay Communication Controller (FlexRAY) 26.6.6.4 Double Transmit Message Buffer The section provides a detailed description of the functionality of the double transmit message buffers. Double transmit message buffers are used by the application to provide the controller with the message data to be transmitted over the FlexRay Bus.
Page 729 FlexRay Communication Controller (FlexRAY) Commit Side Transmit Side Message Buffer Header Field: Frame Header Message Buffer Header Field: Frame Header Message Buffer Header Field: Data Field Offset Message Buffer Header Field: Data Field Offset MBIDXR(2n)[MBIDX] MBIDXR(2n+1)]MBIDX] MBCCSR(2n)[CMT] MBCCSR(2n+1)[CMT] Message Buffer Data Field: DATA[0-N] Message Buffer Data Field: DATA[0-N] Message Buffer Header Field: Slot Status Message Buffer Header Field: Slot Status...
Page 730 FlexRay Communication Controller (FlexRAY) double transmit message buffer are given in Figure 26-133. A description of the states is given in Table 26-108. The description tables also provide the access scheme for the access regions. The status bits MBCCSRn[EDS] and MBCCSRn[LCKS] provide the application with the required message buffer status information.
Page 731 FlexRay Communication Controller (FlexRAY) RESET_STATE HDis Idle CCSu CCSa CCTx CCITx CCSaCCITx CCNf CCMa CCNfCCITx CCMaCCITx Figure 26-133. Double Transmit Message Buffer State Diagram (Transmit Side) A description of the states of the transmit side of a double transmit message buffer is given in Table 26-108.
Page 732 FlexRay Communication Controller (FlexRAY) Table 26-108. Double Transmit Message Buffer State Description (Transmit Side) (continued) MBCCSRn Access Region State Description LCKS Appl. Module CCTx – Message Transmission - Message buffer data transmit. Payload data from buffer transmitted CCSu – Status Update - Message buffer status update. Update of status flags, the slot status field, and the header index.
Page 733 FlexRay Communication Controller (FlexRAY) Module Transitions The module transitions that can be triggered by the controller are described in Table 26-110. The transitions C1 and C2 apply to both sides of the message buffer and are applied at the same time. All other controller transitions apply to the transmit side only.
Page 734 FlexRay Communication Controller (FlexRAY) Table 26-111. Double Transmit Message Buffer Transition Priorities (continued) State Priority Description CCMa TX > STS Transmission Slot Start > Static Slot Start TX > DSS Transmission Slot Start > Dynamic Slot Start 26.6.6.4.4 Message Preparation The application provides the message data through the commit side.
Page 735 FlexRay Communication Controller (FlexRAY) In this mode, the internal message transfer from the commit side to the transmit side is started for a double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the Idle state 2.
Page 736 FlexRay Communication Controller (FlexRAY) Idle CCITx Idle CCITx Idle HLck Idle Idle HLck internal message transfer overwrites non-transmitted message CCITx CCITx Idle Idle Idle search[s+1] slot s slot s+1 slot s+2 Figure 26-135. Internal Message Transfer in Immediate Commit Mode 26.6.6.4.6 Message Transmission For double transmit message buffers, the message buffer search checks only the transmit side part.
Page 737 FlexRay Communication Controller (FlexRAY) The message buffer search within the NIT searches for message buffers assigned or subscribed to slot 1. The message buffer search within slot n searches for message buffers assigned or subscribed to slot n+1. In general, the message buffer search for the next slot n considers only message buffers which are 1.
Page 738 FlexRay Communication Controller (FlexRAY) 26.6.7.1 Message Buffer Cycle Counter Filtering The message buffer cycle counter filter is a value-mask filter defined by the CCFE, CCFMSK, and CCFVAL fields in the Message Buffer Cycle Counter Filter Registers (MBCCFRn). This filter determines a set of communication cycles in which the message buffer is considered for message reception or message transmission.
Page 739 FlexRay Communication Controller (FlexRAY) 26.6.7.4 Message Buffer Search Error If the message buffer search is running while the next message buffer search start event appears, the message buffer search is stopped and the Message Buffer Search Error Flag MSB_EF is set in the Error Flag Register (CHIERFR).
Page 740 FlexRay Communication Controller (FlexRAY) single RX single TX double TX (commit side) double TX (transmit side) Figure 26-137. Message Buffer Reconfiguration Scheme 26.6.9 Receive FIFOs This section provides the functional description of the two receive FIFOs. 26.6.9.1 Overview The two receive FIFOs implement the queued message buffer concept defined by the FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
Page 741 FlexRay Communication Controller (FlexRAY) The FIFO control and configuration data are given in Section 26.6.3.7, Receive FIFO Control and Configuration Data. The configuration of the FIFOs consists of two steps. The first step is the allocation of the required amount of FlexRay memory for the FlexRay window. This includes the allocation of the message buffer header area and the allocation of the message buffer data fields.
Page 742 FlexRay Communication Controller (FlexRAY) 26.6.9.5 FIFO Almost-Full Interrupt Generation If the fifo fill level FLA (FLB) is updated after a frame reception and exceeds the FIFO watermark level WM, i.e. FLA>WM (FLB>WM ), then the FIFO almost-full interrupt flag GIFER[FAFAIF] (GIFER[FAFBIF]) is asserted.If the periodic timer expires, and FIFOA (FIFOB) is not empty, i.e.
Page 743 FlexRay Communication Controller (FlexRAY) 26.6.9.8.1 FIFO Interrupt Flag Update Th FIFO Interrupt Flag Update mode is configured, when the FIFO update mode flag MCR[FUM] is set to 0. In this mode FIFOA (FIFOB) will be updated by 1 entry, when the interrupt flag GIFER[FAFAIF] (GIFER[FAFBIF]) is written with 1 by the application.
Page 744 FlexRay Communication Controller (FlexRAY) Valid Frame Received ( Individual Message Buffer Found Null Frame (vRF!Header!NFIndicator=0 Store Into Message Buffer ( Else Frame ID Value- Mask Rejection Filter Passed Frame ID Else Range Rejection Filter Passed Frame ID Else Range Acceptance Filter Passed Frame Received in Dynamic Segment...
Page 745 FlexRay Communication Controller (FlexRAY) A received frame passes the FIFO filtering if it has passed all three type of filter. 26.6.9.9.1 RX FIFO Frame ID Value-Mask Rejection Filter The frame ID value-mask rejection filter is a value-mask filter and is defined by the fields in the Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR) and the...
Page 746 FlexRay Communication Controller (FlexRAY) acceptance filters if either no acceptance filter is enabled, or, for at least one of the enabled RX FIFO Frame ID Range acceptance filters, i.e. RFRFCTR.FiMD = 0 and RFRFCTR.FiEN = 1, Equation 26-17 fulfilled.  ...
Page 747 FlexRay Communication Controller (FlexRAY) FlexRay FR_A_RX reg(A) FlexRay Channel FlexRay Bus Driver FR_A_TX channel 0 Channel A FR_A_TX_EN cfg(A) cCrcInit[A] FR_B_RX reg(B) FlexRay Channel FlexRay Bus Driver FR_B_TX channel 1 Channel B FR_B_TX_EN cfg(B) cCrcInit[B] Figure 26-139. Dual Channel Device Mode 26.6.10.2 Single Channel Device Mode The single channel device mode supports devices that have only one FlexRay port available.
Page 748 FlexRay Communication Controller (FlexRAY) FlexRay FR_A_RX reg(A) FlexRay Channel FlexRay Bus Driver FR_A_TX channel A Channel A FR_A_TX_EN cfg(A) cCrcInit[A] FR_B_RX reg(B) FR_B_TX channel B FR_B_TX_EN cfg(B) cCrcInit[B] Figure 26-140. Single Channel Device Mode (Channel A) FlexRay FR_A_RX reg(A) FlexRay Channel FlexRay Bus Driver FR_A_TX channel A...
Page 749 FlexRay Communication Controller (FlexRAY) NOTE The values provided in the EOC_AP and ERC_AP fields are the values that were written from the application most recently. If these value were already applied, they will not be applied in the current cycle pair again. If the offset correction applied in the NIT of cycle 2n+1 shall be affect by the external offset correction, the EOC_AP field must be written to after the start of cycle 2n and before the end of the static segment of cycle 2n+1.
Page 750 FlexRay Communication Controller (FlexRAY) 26.6.12.1 Sync Frame ID Table Content The Sync Frame ID Table is a snapshot of the protocol related variables vsSyncIdListA vsSyncIdListB for each even and odd communication cycle. This table provides a list of the frame IDs of the synchronization frames received on the corresponding channel and cycle that are used for the clock synchronization.
Page 751 FlexRay Communication Controller (FlexRAY) While the protocol is in POC:config state, the application must program the offsets for the tables into the Sync Frame Table Offset Register (SFTOR). 26.6.12.4 Sync Frame ID and Sync Frame Deviation Table Generation The application controls the generation process of the Sync Frame ID and Sync Frame Deviation Tables into the FlexRay memory using the Sync Frame Table Configuration, Control, Status Register (SFTCCSR).
Page 752 FlexRay Communication Controller (FlexRAY) After reading all the data from the locked tables, the application must unlock the table by writing to the even table lock trigger SFTCCSR.ELKT again. The even table lock status bit SFTCCSR.ELKS is reset immediately. If the sync frame table generation is disabled, the table valid bits SFTCCSR[EVAL] and SFTCCSR[EVAL] are reset when the counter values in the Sync Frame Counter Register (SFCNTR) updated.
Page 753 FlexRay Communication Controller (FlexRAY)   Eqn. 26-19 PSR0 PROTSTATE POC:normal active   Eqn. 26-20 MTSACRF MTE     & MTSACFR CYCCNTMSK  CYCCNT & MTSACFR CYCCNTMSK MTSACFR CYCCNTVAL Eqn. 26-21 The MTS is transmitted over channel B in the communication cycle with number CYCCNT, if Equation 26-19, Equation...
Page 754 FlexRay Communication Controller (FlexRAY) globally disabled (the SFFE control bit in the Module Configuration Register (MCR) is cleared), all received synchronization frames are considered for clock synchronization. If a received synchronization frame did not pass at least one of the two filters, this frame is processed as a normal frame and is not considered for clock synchronization.
Page 755 FlexRay Communication Controller (FlexRAY) 2. Read STBCSR. The SEL field provides N and the ENB and STBPSEL fields provides the settings for signal N. 26.6.16.2 Strobe Signal Timing This section provides detailed timing information of the strobe signals with respect to the protocol engine clock.
Page 756 FlexRay Communication Controller (FlexRAY) 26.6.17.1 Absolute Timer T1 The absolute timer T1 has the protocol cycle count and the macrotick count as the time base. The timer 1 interrupt flag TI1_IF in the Protocol Interrupt Flag Register 0 (PIFR0) is set at the macrotick start event, Equation 26-28 Equation 26-29 are fulfilled.
Page 757 FlexRay Communication Controller (FlexRAY) is described in Table 26-116. The PE provides the slot status vector within the first macrotick after the end of the related slot/window/NIT, as shown in Figure 26-148. slot 1 static segment dynamic segment symbol window communication cycle Figure 26-148.
Page 758 FlexRay Communication Controller (FlexRAY) Table 26-116. Slot Status Content Status Content static / slot related status dynamic vSS!ValidFrame – valid frame received Slot vSS!SyntaxError – syntax error occurred while receiving vSS!ContentError– content error occurred while receiving vSS!BViolation – boundary violation while receiving for slots in which the module transmits: vSS!TxConflict –...
Page 759 FlexRay Communication Controller (FlexRAY) 26.6.18.2 Protocol Status Registers Protocol Status Register 2 (PSR2) provides slot status information about the Network Idle Time NIT and the Symbol Window. The Protocol Status Register 3 (PSR3) provides aggregated slot status information. 26.6.18.3 Slot Status Registers The eight slot status registers, Slot Status Registers (SSR0–SSR7), can be used to observe the status of...
Page 760 FlexRay Communication Controller (FlexRAY) The increment condition for each slot status counter consists of two parts, the frame related condition part and the slot related condition part. The internal slot status counter SSCRn_INT is incremented if at least one of the conditions is fulfilled: 1.
Page 761 FlexRay Communication Controller (FlexRAY) 26.6.19.1 System Bus Illegal Address Access If the system bus detects an controller access to an illegal address, the controller receives a notification from the system bus about this event and sets the ILSA_EF flag in the CHI Error Flag Register (CHIERFR).
Page 762 FlexRay Communication Controller (FlexRAY) 26.6.19.4 Freeze after System Bus Failure If the SBFF bit in the Module Configuration Register (MCR) is set to 1, the controller will go into the freeze mode immediately after the occurrence of one of the system bus access failures. 26.6.20 Interrupt Support The controller provides 172 individual interrupt sources and five combined interrupt sources.
Page 763 FlexRay Communication Controller (FlexRAY) 26.6.20.2 Combined Interrupt Sources Each combined interrupt source generates an interrupt request only when at least one of the interrupt sources that is combined generates an interrupt request. 26.6.20.2.1 Receive Message Buffer Interrupt The combined receive message buffer interrupt request RBIRQ is generated when at least one of the individual receive message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable bit GIFER.RBIE is set.
Page 764 FlexRay Communication Controller (FlexRAY) Interrupt Sources Interrupt Signals n = # Message Buffers MBCCSRn[MBIF] & MBCCSRn[MBIE] CHIER[15:0] & GIFER[CHIE] PIFR0[15:0] & PIER0[15:0] PIFR1[15:0] & PIER1[15:0] MBCCSRn[MTD] GIFER[RBIF] RBIRQ & & GIFER[RBIE] Receive GIFER[TBIF] TBIRQ & & GIFER[TBIE] Transmit GIFER[CHIF] CHIIRQ GIFER[PRIF] PRTIRQ &...
Page 765 FlexRay Communication Controller (FlexRAY) Figure 26-151. Interrupt Sources Combined Interrupt Flags n = # Message Buffers MBCCSRn[MTD] CIFR[TBIF] & MBCCSRn[MBIF] Transmit CIFR[RBIF] & Receive CHIER[15:0] CIFR[CHIF] PIFR0[15:0] CIFR[PRIF] PIFR1[15:0] CIFR[MIF] GIFER[FAFAIF] GIFER[FAFBIF] GIFER[WUPIF] CIFR[FAFAIF] CIFR[FAFBIF] CIFR[WUPIF] Figure 26-152. Scheme of combined interrupt flags 26.6.21 Lower Bit Rate Support The controller supports a number of lower bit rates on the FlexRay bus channels.
Page 766 FlexRay Communication Controller (FlexRAY) Table 26-117. FlexRay Channel Bit Rate Control FlexRay Channel Bit Rate MCR.BITRATE [Mbit/s] 10.0 25.0 12.5 25.0 12.5 25.0 25.0 50.0 50.0 NOTE The bit rate of 8 Mbit/s is not defined by the FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
Page 767 FlexRay Communication Controller (FlexRAY) 26.7.1.2 Protocol Initialization This section describes the protocol related initialization steps. 1. Configure the Protocol Engine. a) issue CONFIG command via Protocol Operation Control Register (POCR) b) wait for POC:config Protocol Status Register 0 (PSR0) c) configure the PCR0,..., PCR30 registers to set all protocol parameters 2.
Page 768 FlexRay Communication Controller (FlexRAY) The controller uses a sequential search algorithm to determine the individual message buffer assigned or subscribed to the next slot. This search must be finished within one FlexRay slot. The shortest FlexRay slot is an empty dynamic slot. An empty dynamic slot is a minislot and consists of gdMinislot macroticks with a nominal duration of gdMacrotick.
Page 769 FlexRay Communication Controller (FlexRAY) If the command execution block of the PE is idle, it selects the next accepted protocol command with the highest priority from the current protocol command vector according to the protocol control command priorities given in Table 26-119.
Page 770 FlexRay Communication Controller (FlexRAY) Table 26-120. Transmit Buffer Configuration Register Field Value Description used only for double buffers MBCCSRt single transmit buffer transmit buffer event transition mode assigned to channel A not assigned to channel B MBCCFRt CCFE cycle counter filter enabled CCFMSK 000011 cycle set = {4n} = {0,4,8,12,...}...
Page 771 FlexRay Communication Controller (FlexRAY) 26.7.5.2 Behavior in Static Segment In this case, both message buffers are assigned to a slot S in the static segment. The configuration of a transmit buffer for a static slot S assigns this slot to the node as a transmit slot. The FlexRay protocol requires: •...
Page 772 FlexRay Communication Controller (FlexRAY) b) for the cycles in the set {4n + 2}, which is assigned to the receive buffer only, the receive buffer will be found and the node can receive data. The receive and transmit cycles are shown in Figure 26-153 Figure 26-154.
Page 773 Chapter 27 Media Local Bus (MLB) 27.1 Introduction The MediaLB (MLB) is a multiplexed bus protocol defined by Standard Microsystems Semiconductor Company (SMSC) to transfer multimedia data between the Media-Oriented Systems Transport (MOST) ring and supporting system level ICs. It supports the complete MLB specification. This module offers a serial to parallel conversion of the 3-pin MediaLB signals into 32-bit parallel words and vice versa for transfer to system memory.
Page 774 Media Local Bus (MLB) 27.1.2 Features • 3-pin MediaLB interface supported • Support for as many as 16 logical channels and as many as 31 physical channels running at a maximum speed of 1024Fs • Programmable MediaLB clock frequency — 256 Fs = 12.3 megabits per second @ Fs = 48 kHz —...
Page 775 Media Local Bus (MLB) MLB device that it can transmit data for that logical channel during the next physical channel slot. One quadlet later, the transmitting MLB device send out a MLB command byte on the signal information line and the corresponding data on the data line. All other MLB devices (including the controller) have already compared the logical channel address with their internal table of addresses to determine if they are the intended recipient of the data on this logical channel.
Page 776 Media Local Bus (MLB) Table 27-3. Signal Properties Signal Port SIU_PCR Register Function I/O Reset Pull MLBCLK SIU_PCR144 MLB Clock Down MLBSIG SIU_PCR145 MLB Signal (control/status) I/O Down MLBDAT SIU_PCR146 MLB Data Down Detailed signal descriptions for the MLB peripheral can be found in Table 27-4.
Page 777 Media Local Bus (MLB) Table 27-5. Configuration Registers (continued) Offset from MLB_BASE Name Access 0xC3F8_4000) 0x0000_001C VCCR—Version Control Configuration Register 0x0000_0020 SBCR—Synchronous Base Address Configuration Register 0x0000_0024 ABCR—Asynchronous Base Address Configuration Register 0x0000_0028 CBCR—Control Base Address Configuration Register 0x0000_002C IBCR—Isochronous Base Address Configuration Register 0x0000_0030 CICR—Channel Interrupt Configuration Register Table 27-6.
Page 778 Media Local Bus (MLB) Table 27-7. MLB Memory Map (continued) Offset from MLB_BASE Register Access Reset Value Section/Page 0xC3F8_4000) 0x0048 CCBCR0—Channel 0 Current Buffer Configuration Register 0x0000_0000 27.3.2.13/27-22 0x004C CNBCR0—Channel 0 Next Buffer Configuration Register 0x0000_0000 27.3.2.14/27-23 0x0050 CECR1—Channel 1 Entry Configuration Register 0x0000_0000 27.3.2.11/27-17 0x0054...
Page 779 Media Local Bus (MLB) Table 27-7. MLB Memory Map (continued) Offset from MLB_BASE Register Access Reset Value Section/Page 0xC3F8_4000) 0x00C4 CSCR8—Channel 8 Status Configuration Register 0x8000_0000 27.3.2.12/27-19 0x00C8 CCBCR8—Channel 8 Current Buffer Configuration Register 0x0000_0000 27.3.2.13/27-22 0x00CC CNBCR8—Channel 8 Next Buffer Configuration Register 0x0000_0000 27.3.2.14/27-23 0x00D0...
Page 780 Media Local Bus (MLB) Table 27-7. MLB Memory Map (continued) Offset from MLB_BASE Register Access Reset Value Section/Page 0xC3F8_4000) 0x0140–0x027F Reserved 0x0280 LCBCR0—Local Channel 0 Buffer Configuration Register 0x0803_E000 27.3.2.15/27-24 0x0284 LCBCR1—Local Channel 1 Buffer Configuration Register 0x0803_E020 27.3.2.15/27-24 0x0288 LCBCR2—Local Channel 2 Buffer Configuration Register 0x0803_E040 27.3.2.15/27-24...
Page 781 Media Local Bus (MLB) Offset: MLB_BASE + 0x0000 Access: User read/write MDE LBM MCS[1:0] MLE MHRE MRS Reset MDA[8:1] Reset Figure 27-2. Device Control Configuration Register (DCCR) Table 27-8. DCCR Field Descriptions Field Description MLB Device Enable. When set, enables the MLB Interface based on the other bits in the register. 0 MLB device disabled.
Page 782 Media Local Bus (MLB) Table 27-8. DCCR Field Descriptions (continued) Field Description MLB Software Reset. When set, resets the MLB physical and link layer logic. Hardware clears this bit automatically. 0 MLB device is not reset by software. 1 MLB device is reset by software. MLB Device Address.
Page 783 Media Local Bus (MLB) Table 27-9. SSCR Field Descriptions (continued) Field Description SDML System Detects MLB Lock. This bit is set to indicate that the MLB Device has locked to the MLB frame. Detecting a MLB lock generates a maskable system interrupt to system software. Once set, this bit is sticky until cleared by software.
Page 784 Media Local Bus (MLB) Offset: MLB_BASE + 0x0008 Access: User read-only MSD[31:16] Reset MSD[15:0] Reset Figure 27-4. System Data Configuration Register (SDCR) Table 27-10. SDCR Field Descriptions Field Description MLB System Data. This register is loaded with the data from MLBDAT during the System Channel quadlet. 27.3.2.4 System Mask Configuration Register (SMCR) The System Mask Configuration register (SMCR) allows system software to mask system status...
Page 785 Media Local Bus (MLB) Table 27-11. SMCR Field Descriptions Field Description SMMU System Masks MLB Unlock. When set, this bit masks system interrupts generated when a MLB unlock is detected. At reset, MLB unlock events are masked (SMMU = 1). 0 MLB unlock system interrupt is enabled.
Page 786 Media Local Bus (MLB) Table 27-12. VCCR Field Descriptions Field Description User Major Revision. For first release of the PXN20, the value is 0x03. [7:0] User Minor Revision. For first release of the PXN20, the value is 0x00. [7:0] MLB Device Major Revision. For first release of the PXN20, the value is 0x02. [7:0] MLB Device Minor Revision.For first release of the PXN20, the value is 0x02.
Page 787 Media Local Bus (MLB) Offset: MLB_BASE + 0x0024 Access: User read/write ARBA[31:16] Reset ATBA[31:16] Reset Figure 27-8. Asynchronous Base Address Configuration Register (ABCR) Table 27-14. ABCR Field Descriptions Field Description ARBA Asynchronous Receive Base Address. This base address is shared by all asynchronous RX channels and defines [31:16] the upper 16 bits of the 32-bit system memory address for these channels.
Page 788 Media Local Bus (MLB) Table 27-15. CBCR Field Descriptions Field Description CRBA Control Receive Base Address. This base address is shared by all control RX channels and defines the upper 16 [31:16] bits of the 32-bit system memory address for these channels. CTBA Control Transmit Base Address.
Page 789 Media Local Bus (MLB) Offset: MLB_BASE + 0x0030 Access: User read-only Reset CSU[15:0] Reset Figure 27-11. Channel Interrupt Configuration Register (CICR) Table 27-17. CICR Field Descriptions Field Description Channel Status Update for Logical Channels 15 through 0. When set, these bits indicate that hardware has [15:0] generated an interrupt for the appropriate channel.
Page 790 Media Local Bus (MLB) Table 27-18. CECRn Field Descriptions Field Description Channel n Enable. 0 Channel n disabled. 1 Channel n enabled. Channel n Transmit Select. 0 Receive. 1 Transmit. CT[1:0] Channel n Type Select. 00 Synchronous. 01 Isochronous. 10 Asynchronous. 11 Control.
Page 791 Media Local Bus (MLB) Table 27-18. CECRn Field Descriptions (continued) Field Description FSCD Frame Synchronization Channel Disable. When set, disables this logical channel (set CECHRn[CE] = 0) when Lost Frame Synchronization occurs. This field is valid for synchronous channels only. 0 Do not disable this logical channel when frame synchronization is lost.
Page 792 Media Local Bus (MLB) Offset: 0x0044 (CSCR0) 0x0084 (CSCR4) 0x00C4 (CSCR8) 0x0104 (CSCR12) Access: User read/write 0x0054 (CSCR1) 0x0094 (CSCR5) 0x00D4 (CSCR9) 0x0114 (CSCR13) 0x0064 (CSCR2) 0x00A4 (CSCR6) 0x00E4 (CSCR10) 0x0124 (CSCR14) 0x0074 (CSCR3) 0x00B4 (CSCR7) 0x00F4 (CSCR11) 0x0134 (CSCR15) IVB[1:0] GIRB/ Reset...
Page 793 Media Local Bus (MLB) Table 27-19. Channel n Status Configuration Register Field Descriptions (continued) Field Description Next Buffer Ready. System software should set this bit when all the registers, data, and program memory variables are setup and ready to transmit or receive data using DMA. For TX data, the system memory buffer should also be filled.
Page 794 Media Local Bus (MLB) Table 27-19. Channel n Status Configuration Register Field Descriptions (continued) Field Description Buffer Error. When set, this bit indicates that either a TX channel has detected a buffer underflow (e.g. attempted to pop data from an empty buffer), or an RX channel has detected a buffer overflow (e.g. attempted to push data onto a full buffer).
Page 795 Media Local Bus (MLB) Offset: 0x0048 (CCBCR0) 0x0088 (CCBCR4) 0x00C8 (CCBCR8) 0x0108 (CCBCR12) Access: User read/write 0x0058 (CCBCR1) 0x0098 (CCBCR5) 0x00D8 (CCBCR9) 0x0118 (CCBCR13) 0x0068 (CCBCR2) 0x00A8 (CCBCR6) 0x00E8 (CCBCR10) 0x0128 (CCBCR14) 0x0078 (CCBCR3) 0x00B8 (CCBCR7) 0x00F8 (CCBCR11) 0x0138 (CCBCR15) BCA[15:0] Reset BFA[15:0]...
Page 796 Media Local Bus (MLB) Offset: 0x004C (CNBCR0) 0x008C (CNBCR4) 0x00CC (CNBCR8) 0x010C (CNBCR12) Access: User read/write 0x005C (CNBCR1) 0x009C (CNBCR5) 0x00DC (CNBCR9) 0x011C (CNBCR13) 0x006C (CNBCR2) 0x00AC (CNBCR6) 0x00EC (CNBCR10) 0x012C (CNBCR14) 0x007C (CNBCR3) 0x00BC (CNBCR7) 0x00FC (CNBCR11) 0x013C (CNBCR15) BSA[15:0] Reset BEA[15:0]...
Page 797 Media Local Bus (MLB) LCBCR3). Writing to this register while the corresponding logical channel is enabled may result in unexpected behavior. Offset: 0x0280 (LCBCR0) 0x0290 (LCBCR4) 0x02A0 (LCBCR8) 0x02B0 (LCBCR12) Access: User read/write 0x0284 (LCBCR1) 0x0294 (LCBCR5) 0x02A4 (LCBCR9) 0x02B4 (LCBCR13) 0x0288 (LCBCR2) 0x0298 (LCBCR6) 0x02A8 (LCBCR10)
Page 798 Media Local Bus (MLB) Table 27-22. Local Channel n Buffer Configuration Register Field Descriptions Field Description BD[8:0] Buffer Depth. This field defines the depth of the local channel buffer in the local buffer RAM in increments of 4 quadlets. At reset, the LCBCHn[BD[8:0]] field is loaded with 0x01F, or 128 quadlets. 0x000 –...
Page 799 Media Local Bus (MLB) various parameters and control the operation of the MLB Device. The registers are accessed through the peripheral bus. • MLB Channel Buffer. Implements the interface between the MLB Device and a single-port SRAM. Functionality of the MLB Channel Buffer logic block includes: —...
Page 800 Media Local Bus (MLB) serial format required by the MLB interface. Data is transferred over the MLB in quadlets (32-bit words). The MLB protocol supports as many as 32 quadlets per frame. 27.4.1 Clocking Requirements The system clock (SYS_CLK) requirements for operation are shown in Table 27-23.
Page 801 Media Local Bus (MLB) Table 27-24. MLB Interrupts PXN20 Interrupt Name Interrupt Flag Bits Interrupt Mask Bits Interrupt Vector MLB Logical Channel 4 Interrupt CSCR4[20:31] CECR4[9:15] MLB Logical Channel 5 Interrupt CSCR5[20:31] CECR5[9:15] MLB Logical Channel 6 Interrupt CSCR6[20:31] CECR6[9:15] MLB Logical Channel 7 Interrupt CSCR7[20:31] CECR7[9:15]...
Page 802 Media Local Bus (MLB) 27.4.4 Local Channel Buffer RAM A single-port RAM is used to implement the memory space for local channel buffering. The size of the RAM is 2k x 36-bits (1 quadlet of data; 4-bit tag). The initial start address and depth values for the logical channels buffered in the RAM are controlled via the LCBCRn.
Page 803 Media Local Bus (MLB) 27.4.5 Channel Arbiter The MLB Device includes a DMA Controller with a Host Bus that can access system memory. The channel arbiter logic of the MLB Device, arbitrates requests between the different logical channel requests. Some of the functions of the channel arbiter include: •...
Page 804 Media Local Bus (MLB) 27.4.6 DMA Controller (Ping-Pong Buffering) Using the MLB DMA Controller with ping-pong buffering dictates a particular method used for transferring data between hardware channels and system memory. When the MLB hardware channels are configured in this mode, the CCBCRn and CNBCRn registers are used to configure and monitor the system memory Current Buffer and Next Buffer, respectively.
Page 805 Media Local Bus (MLB) Multi-Packet Buffering Example (Shows RX/TX handling of Asynchronous/Control Packets using the Current Buffer) Note 2 Packet 1 (First Packet) Note 3 internal register * RX handling only Legend Packet 2 = 16-bit address pointer Note 1 Note 4 = channel interrupt Packet 3...
Page 806 Media Local Bus (MLB) • The CCBCRn[BCA] field is loaded into an internal hardware register (not visible to system software) at the start of each incoming asynchronous or control RX packet. If the packet is later aborted (caused by AsyncBreak, ControlBreak, ReceiverBreak, or ReceiverProtocolError), CCBCRn[BCA] is restored with the address pointer in the internal hardware register.
Page 807 Media Local Bus (MLB) • A Buffer Done interrupt is generated (CSCRn[STS[2]] set) when the last quadlet from the last packet (in the Current Buffer) has been successfully transmitted. (See Note 6 in Figure 27-19). Single-packet buffering of asynchronous and control TX packets should be handled in the same manner described for multi-packet buffering.
Page 808 Media Local Bus (MLB) Isochronous/Synchronous Data Buffering Examples (Shows RX/TX handling of Isochronous/Synchronous Data using the Current Buffer) Note 2 Isochronous Packet 1 (First Packet) Legend Isochronous Packet 2 Note 3 = 16-bit address pointer Note 1 Isochronous Synchronous Packet 3 Data = channel interrupt Isochronous...
Page 809 Media Local Bus (MLB) While processing the circular buffer, the CSCRn[RDY] bit is not automatically cleared by hardware, as it is with ping-pong buffering. For circular buffer, the CSCRn[RDY] bit can only be cleared by software through the peripheral bus interface. Once CNBCRn[BSA] and CNBCRn[BEA] are initially loaded, software should set the CSCRn[RDY] bit to initiate buffer processing.
Page 810 Media Local Bus (MLB) 27.4.8 Streaming Channel Frame Synchronization Certain types of streaming applications require data to be synchronous with the MLB frame, including: stereo, 5.1 audio, and Generic Synchronous Packet Format (GSPF) DTCP. The MLB Streaming Channel Frame Synchronization feature provides this option. For example, 24-bit stereo channels require two MLB physical channels (PC) to transmit left (0xLLLLLn) and right (0xRRRRRn) speaker data.
Page 811 Media Local Bus (MLB) Additionally, software may instruct the MLB to automatically disable a logical channel when MLB frame synchronization is lost. To enable this feature, software must set CSCLRn[FSCD], which causes hardware to automatically clear the Channel Enable bit (CECHRn[CE]) when synchronization is lost. Frame synchronization is not supported for asynchronous, control, or isochronous channels.
Page 812 Media Local Bus (MLB) 27.5.1 Main Loop MLB module System Reset InitDevice ReturnInitDevice MediaLB Lock? Initialize MLB Module Hardware Channels n = 0 ChgChann ReturnChgChan InitChann ReturnInitChan n < num_of_chans? Background Loop ProcessCint CINT == 1? ReturnCint SINT ProcessSint == 1? ReturnSint Figure 27-23.
Page 813 Media Local Bus (MLB) 27.5.2 Initialize Device InitDevice Set system interrupt mask SMCR[31:27] Write data to SMCR at PBI address 0x03 Enable MLB module DCCR[MDE] Disable loop-back test mode DCCR[LBM] Select MediaLB clock speed DCCR MCS[1:0] Select MediaLB pin mode DCCR[4] Set system endianness DCCR[MLE]...
Page 814 Media Local Bus (MLB) 27.5.3 Initialize Channel InitChan(n) Determine channel direction CECRn[TR] Determinechannel type CECRn[CT[1:0]] Isochronous channel? Determine isochronous flow control mechanism CECRn[FSE] Determine isochronouspacket length CECRn[IPL[7:0]] For DMA Mode (ping-pong buffering), the interrupt mask bits could be set as follows: 4: 0 –...
Page 815 Media Local Bus (MLB) InitDMABuffern Determine next buffer start address CNBCRn[15:0] Determine next buffer end address CNBCRn[31:16] Write data to CNBCRn at PBI address 0x13 + 4 * n Ensure buffer is either filled for transmission or ready for data reception Set RDY to 1 in CSCRn[15] at IO address 0x11 + 4 * n ReturnDMABuffer...
Page 816 Media Local Bus (MLB) 27.5.4 Channel Interrupts ProcessCint Read interrupts from CICR at PBI address 0x0C n = 0 Read channel status from CSCRn CICRn at PBI address 0x11 + 4 * n == 1? Ping-Pong Buffering? ProcCintDMA ProcCintDMACir n ++ ReturnCintDMA ReturnCintDMACir CLEAR INTERRUPTS:...
Page 817 Media Local Bus (MLB) ProcCintDMA Buffer overflow for RX CSCRn[BE] Buffer underflow for TX == 1? Disable channel CSCRn[HBE] Host bus error and notify application == 1? CSCRn[CBS] DMA current buffer started == 1? initDMABuffer ReturnDMABuffer CSCRn[CBD] == 1? DMA current buffer done Protocol error detected on MediaLB CSCRn[CBPE] == 1?
Page 818 Media Local Bus (MLB) ProcCintDMA (Part 2) CSCRn[PBD] == 1? DMA current buffer done Protocol error detected on MediaLB CSCRn[PBPE] == 1? during previous buffer Notify application CSCRn[PBDB] Break request detected on MediaLB == 1? during previous buffer Notify application Process previous buffer in system memory ReturnCintDMA...
Page 819 Media Local Bus (MLB) ProcCintDMACir Buffer overflow for RX CSCRn[BE] Buffer underflow for TX == 1? Disable channel CSCRn[HBE] Host bus error and notify application == 1? Protocol error detected on MediaLB CSCRn[CBPE] == 1? during current buffer Notify application CSCRn[CBDB] Break received on MediaLB == 1?
Page 820 Media Local Bus (MLB) 27.5.5 System Interrupts ProcessSint Read data from SSCR at PBI address 0x01 Read data from CSDCR SSCR[SDR] Detect system reset command == 1? at PBI address 0x02 SDCR == SDCR DeviceAddress? SSCR[SDNL] == 0? Detect network lock == 1? Reset Notify application...
Page 821 Media Local Bus (MLB) PXN20 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-49...
Page 822 Media Local Bus (MLB) PXN20 Microcontroller Reference Manual, Rev. 1 27-50 Freescale Semiconductor...
Page 823 Chapter 28 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.1 Introduction The eMIOS200 provides functionality to generate or measure time events. The eMIOS200 is implemented with its own configuration of timer channels to suit the target applications needs, while providing a consistent user interface with previous eMIOS implementations. The PXN20 has one eMIOS200 module that implements 16-bit counters.
Page 824 Enhanced Modular Input/Output Subsystem (eMIOS200) Enhanced Modular I/O System Channel[23] Channel (eMIOS200) EMIOS[23] Type A Submodules Channel[22] Channel EMIOS[22] Type C Interface • • Counter • • • • Buses (Time Channel[16] Bases) Channel EMIOS[16] Type A Global Time Base Enable Global Time Base Channel[15] Bit (GTBE) Output...
Page 825 Enhanced Modular Input/Output Subsystem (eMIOS200) — 16-bit internal counter — Internal prescaler — Selectable time base — Can generate its own time base • Four 16-bit-wide counter buses — Counter bus A can be driven by unified channel 23 — Counter buses B, C, D, and E are driven by unified channels 0, 8, 16, and 24, respectively —...
Page 826 Enhanced Modular Input/Output Subsystem (eMIOS200) eMIOS A—PXN21 eMIOS A—PXN20 Channel31 Channel23 Channel30 Channel22 IP Bus IP Bus Interface Interface Channel29 Channel21 Channel28 Channel20 Global Global Clock Clock Channel27 Channel19 Prescaler Prescaler Channel26 Channel18 Channel25 Channel17 Channel24 Channel16 Channel23 Channel15 Channel22 Channel14 Channel21 Channel13...
Page 827 Enhanced Modular Input/Output Subsystem (eMIOS200) accumulation (PEC, PEA) and Quadrature Decode (QDEC). On the PXN21, five of these channels are implemented on the device. On the PXN20, four of these channels are implemented. 28.1.4.2 Type B: Complex Channels These complex channel types offer most of the modes already available on the counter channels. This channel type includes Center aligned PWM modes with deadtime to allow support for motor control applications, and may be combined with the quadrature decode of Type A channels.
Page 828 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.2 External Signal Description Refer to Table 3-1 Section 3.4, Detailed Signal Description, for detailed signal descriptions. Each channel has one external signal, eMIOS[n]. Through the pad configuration register (SIU_PCRn[PA]), you can choose to have a pin’s function be the eMIOS channel in either or both places as described in Table 28-6.
Page 829 Enhanced Modular Input/Output Subsystem (eMIOS200) Table 28-3. eMIOS200 Memory Map Offset from EMIOS_BASE Register Access Reset Value Section/Page (0xFFFE_4000) Global Registers 0x0000 EMIOS_MCR—Module Configuration Register 0x0000_0000 28.3.2.1/28-9 0x0004 EMIOS_GFR—Global FLAG Register 0x0000_0000 28.3.2.2/28-10 0x0008 EMIOS_OUDR—Output Update Disable Register 0x0000_0000 28.3.2.3/28-11 0x000C EMIOS_UCDIS—Stop (Disable) Channel Register 0x0000_0000...
Page 830 Enhanced Modular Input/Output Subsystem (eMIOS200) Table 28-3. eMIOS200 Memory Map (continued) Offset from EMIOS_BASE Register Access Reset Value Section/Page (0xFFFE_4000) Unified Channel 3–31 Registers 0x0080–0x041F Same as other Channel Registers (e.g. EMIOS_CADR[2], — — — EMIOS_CBDR[2], etc.) 0x0420–0x3FFF Reserved Note that R/W registers may contain some read-only or write-only bits. The alternate address register provides and alternate read-only address to access A2 channel registers in pulse edge counting (PEC) and windowed programmable time accumulation (WPTA) modes.
Page 831 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.3.2.1 eMIOS200 Module Configuration Register (EMIOS_MCR) The EMIOS_MCR contains global control bits for the eMIOS200 block. Offset: EMIOS_BASE + 0x0000 Access: User read/write MDIS FRZ GTBE GPREN Reset GPRE[0:7] Reset Figure 28-3. eMIOS200 Module Configuration Register (EMIOS_MCR) Table 28-5.
Page 832 Enhanced Modular Input/Output Subsystem (eMIOS200) Table 28-5. EMIOS_MCR Field Descriptions (continued) Field Description GPREN Global Prescaler Enable Bit. The GPREN bit enables the prescaler counter. 0 Prescaler disabled (no clock) and prescaler counter is cleared. 1 Prescaler enabled. GPRE Global Prescaler Bits. The GPRE bits select the clock divider value for the global prescaler. GPRE Divide Ratio 0000_0000...
Page 833 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.3.2.3 eMIOS200 Output Update Disable Register (EMIOS_OUDR) Offset: EMIOS_BASE + 0x0008 Access: User read/write OU31 OU30 OU29 OU28 OU27 OU26 OU25 OU24 OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16 Reset OU15 OU14 OU13 OU12 OU11 OU10 OU9 Reset Figure 28-5.
Page 834 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.3.2.5 eMIOS200 A Register (EMIOS_CADR[n]) Offset: UC[n] base address + 0x0000 Access: User read/write Reset Reset Figure 28-7. eMIOS200 A Register (EMIOS_CADR[n]) Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be assigned to address EMIOS_CADR[n].
Page 835 Enhanced Modular Input/Output Subsystem (eMIOS200) Table 28-9. EMIOS_CADR[n] and EMIOS_CBDR[n] Values Assignment Register Access Operation Mode Write Read Write Read Alternate Read GPIO A1, A2 B1, B2 — SAIC — — SAOC — IPWM — — — — — — DAOC —...
Page 836 Enhanced Modular Input/Output Subsystem (eMIOS200) Depending on the channel configuration it may have an internal counter or not. It means that if at least one mode that requires the counter is implemented, then the counter is present, otherwise it is absent. 28.3.2.8 eMIOS200 Control Register (EMIOS_CCR[n]) Offset: UC[n] base address + 0x000C...
Page 837 Enhanced Modular Input/Output Subsystem (eMIOS200) Table 28-10. EMIOS_CCR[n] Field Descriptions (continued) Field Description UCPRE Prescaler Bits. The UCPRE bits select the clock divider value for the internal prescaler of unified channel. UCPRE Divide Ratio UCPREN Prescaler Enable Bit. The UCPREN bit enables the prescaler counter. 0 Prescaler disabled (no clock) and prescaler counter is loaded with UCPRE value.
Page 838 Enhanced Modular Input/Output Subsystem (eMIOS200) Table 28-10. EMIOS_CCR[n] Field Descriptions (continued) Field Description FORCMB Force Match B Bit. For output modes, the FORCMB bit is equivalent to a successful comparison on comparator B (except that the FLAG bit is not set). This bit is cleared by reset and is always read as 0. This bit is valid for every output operation mode which uses comparator B, otherwise it has no effect.
Page 839 Enhanced Modular Input/Output Subsystem (eMIOS200) Table 28-11. MODE Bits MODE[0:6] Mode Description 000_0000 GPIO (input) General Purpose Input/Output mode (input) 000_0001 GPIO (output) General Purpose Input/Output mode (output) 000_0010 SAIC Single Action Input Capture 000_0011 SAOC Single Action Output Compare 000_0100 IPWM Input Pulse Width Measurement...
Page 840 Enhanced Modular Input/Output Subsystem (eMIOS200) Table 28-11. MODE Bits (continued) MODE[0:6] Mode Description 001_1110 OPWMCB Center Aligned Output Pulse Width Modulation (flag in both edges, trail edge dead-time) 001_1111 OPWMCB Center Aligned Output Pulse Width Modulation (flag in both edges, lead edge dead-time) 010_0000 OPWMB Output Pulse Width Modulation (flag on B1 match, immediate update)
Page 841 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.3.2.9 eMIOS200 Status Register (EMIOS_CSR[n]) Offset: UC[n] base address + 0x0010 Access: User read/write Reset R OVFL UCIN UCOUT FLAG Reset Figure 28-11. eMIOS200 Status Register (EMIOS_CSR[n]) Table 28-12. EMIOS_CSR[n] Field Descriptions Field Description Overrun Bit. The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set. This bit can be cleared by clearing the FLAG bit or by software writing a 1.
Page 842 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.3.2.10 eMIOS200 Alternate A Register (EMIOS_ALTA[n]) UC[n] base address + 0x0014 Access: User read/write ALTA Reset ALTA Reset Figure 28-12. eMIOS200 Alternate A Register (EMIOS_ALTA[n]) The EMIOS_ALTA[n] register provides an alternate read-only address to access A2 channel registers in PEC and WPTA modes only.
Page 843 Enhanced Modular Input/Output Subsystem (eMIOS200) • An output disable input selector, which selects the output disable input signal to be used as output disable Unified Channel ipd_done Clock Programmable ipd_req Prescaler Filter uc_int_flag ips_wdata[31:0] channel_controller biu_channel_en[n] biu_a_en biu_b_en biu_cnt_en biu_control_en RWCB biu_status_en Match Logic...
Page 844 Enhanced Modular Input/Output Subsystem (eMIOS200) EMIOS_CCR/Mode Channel Controller MODEn_en • • • MODE1_en MODE0_en • • • Control Signals Mode 0 Logic Channel Control Signals Mode 1 • • Datapath Logic • • • • • Shared • Logic Control Signals Mode n Logic Figure 28-14.
Page 845 Enhanced Modular Input/Output Subsystem (eMIOS200) In GPIO input mode (MODE = 000_0000),the FLAG generation is determined according to EDPOL and EDSEL bits and the input pin status can be determined by reading the UCIN bit. In GPIO output mode (MODE = 000_0001), the unified channel is used as a single output port pin and the value of the EDPOL bit is permanently transferred to the output flip-flop.
Page 846 Enhanced Modular Input/Output Subsystem (eMIOS200) Edge detect Edge detect Edge detect EDSEL = 1 EDPOL = x Input Signal 0x001000 0x001001 0x001102 0x001103 0x001104 0x001105 0x001106 0x001107 0x001108 Selected Counter Bus FLAG Set Event FLAG Pin/Register FLAG Clear A2 (Captured) Value 0xxxxxx 0x001000 0x001103...
Page 847 Enhanced Modular Input/Output Subsystem (eMIOS200) EDSEL = 1 Update to EDPOL = x A1 Match A1 Match A1 Match Output Flip-Flop Selected 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 Counter Bus FLAG Set Event 0xxxxxxx 0x001000 0x001000 0x001000 0x001000 A1 Value Note: EMIOS_CADR[n] = A2 Figure 28-18.
Page 848 Enhanced Modular Input/Output Subsystem (eMIOS200) In order to guarantee coherent access, reading EMIOS_CADR[n] forces B1 to be updated with the content of register A1. At the same time transfers between B2 and B1 are disabled until the next read of EMIOS_CBDR[n] register.
Page 849 Enhanced Modular Input/Output Subsystem (eMIOS200) Read EMIOS_CADR[ n] Read EMIOS_CBDR[n] EDPOL = 1 Input Signal Selected 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0 Counter Bus FLAG Set Event A2 (Captured) 0xxxxxxx 0x001100 0x001525 Value B2 (Captured) 0xxxxxxx 0x001000 0x001250 0x0016A0 Value A1 Value 0xxxxxxx 0x001000...
Page 850 Enhanced Modular Input/Output Subsystem (eMIOS200) The input pulse period is calculated by subtracting the value in B1 from A2. Figure 28-22 shows how the unified channel can be used for input period measurement. EDPOL = 1 Input Signal Selected 0x000500 0x001000 0x001100 0x001250...
Page 851 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.4.1.1.6 Double Action Output Compare (DAOC) Mode In the DAOC mode the leading and trailing edges of the variable pulse-width output are generated by matches occurring on comparators A and B, respectively. When the DAOC mode is first selected (coming from GPIO mode) both comparators are disabled. Comparators A and B are enabled by updating registers A1 and B1 respectively and remain enabled until a match occurs on that comparator, when it is disabled again.
Page 852 Enhanced Modular Input/Output Subsystem (eMIOS200) Update to MODE[6] = 1 A1 & B1 A1 Match B1 Match A1 Match B1 Match Output Flip-Flop Selected 0x000500 0x001000 0x001100 0x001000 0x001100 Counter Bus FLAG Set Event A1 Value 0xxxxxxx 0x001000 0x001000 0x001000 B1 Value 0xxxxxxx 0x001100 0x001100...
Page 853 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.4.1.1.7 Pulse/Edge Accumulation (PEA) Mode The PEA mode returns the time taken to detect a desired number of input events. MODE[6] bit selects between continuous or single shot operation. After writing to register A1, the internal counter is cleared on the first input event, ready to start counting input events and the selected timebase is latched into register B2.
Page 854 Enhanced Modular Input/Output Subsystem (eMIOS200) MODE = 000_10000 A1 Match A1 Match EMIOS_CCNTR[n] write to A1 0xFFFFFF 0x001500 0x000000 Time FLAG Pin/Register Selected Counter Bus 0x000090 0x000400 0x001000 0x007000 Input Signal events A1 events no events A1 events 0xxxxxxx 0x001500 A1 Value 0x001500 0x001500...
Page 855 Enhanced Modular Input/Output Subsystem (eMIOS200) Triggering of the internal counter is done by a rising or falling edge or both edges on the input signal. The polarity and the triggering edge is selected by EDSEL and EDPOL bits in EMIOS_CCR[n] register. Register A1 holds the start time and register B1 holds the stop time for the time window.
Page 856 Enhanced Modular Input/Output Subsystem (eMIOS200) MODE = 000_1011 A1 B1 write A1 Match EMIOS_CCNTR[n] A1 Match B1 Match B1 Match amount of events detected amount of events detected 0x000000 Time Flag Pin/Register Selected Counter Bus 0x000090 0x000303 0x000090 0x000303 A1 Value 0x000090 0x000090 0x000090...
Page 857 Enhanced Modular Input/Output Subsystem (eMIOS200) Direction (from UC[n]) MODE[6] = 0 EDPOL = 1 Count (from UC[n – 1]) EMIOS_CCNTR[n] inc/dec + 1 + 1 + 1 + 1 + 1 + 1 + 1 -1 -1 -1 -1 -1 A1 Match A1 Match A1 Write...
Page 858 Enhanced Modular Input/Output Subsystem (eMIOS200) • Internal counter clearing on match start (MODE[0:6] = 001_000b) — External clock is selected if MODE[6] is set. In this case the internal counter clears as soon as the match signal occurs. The channel FLAG is set at the same time the match occurs. Note that by having the internal counter cleared as soon as the match occurs and incremented at the next input event a shorter zero count is generated.
Page 859 Enhanced Modular Input/Output Subsystem (eMIOS200) MODE[4] = 0 Write to A2 Write to A2 A1 Match A1 Match A1 Match A1 Match EMIOS_CCNTR[n] 0xFFFFFF 0x000303 0x000200 0x000000 Time FLAG Pin/Register 0xxxxxxx 0x000303 0x000303 0x000200 0x000200 A1 Value 0x000303 Notes: 1. EMIOS_CADR[n] = A1 A2 = A1 according to OU[n] bit Figure 28-33.
Page 860 Enhanced Modular Input/Output Subsystem (eMIOS200) MODE[4] = 1, the counter changes direction at the A1 match and counts down until it reaches the value one. After it has reached one, it is set to count in up direction again. Register B1 is set to one at mode entering and cannot be changed while this mode is selected.
Page 861 Enhanced Modular Input/Output Subsystem (eMIOS200) A1 Match A1 Match Write to A2 Write to A2 EMIOS_CCNTR[n] 0x000007 0x000006 0x000005 0x000001 Time FLAG Set Event 0x000005 0x000007 A2 Value A1 Value 0x000005 0x000006 0x000007 Figure 28-36. Modulus Counter Buffered (MCB) Up/Down Mode Figure 28-37 shows the A1 register update process in up counter mode.
Page 862 Enhanced Modular Input/Output Subsystem (eMIOS200) Cycle n Cycle n + 1 Cycle n + 2 A1 Match A1 Match Write to A2 Write to A2 EMIOS_CCNTR[n] 0x000006 0x000005 0x000001 Time Selected Counter = 2 A1 Load Signal 0x000006 0x000005 0x000006 A2 Value A1 Value 0x000006...
Page 863 Enhanced Modular Input/Output Subsystem (eMIOS200) System Clock Prescaler EMIOS_CCNTR A1 Match A1 Value 0x000004 Time Negedge B1 Value 0x000008 Detection A1 Match A1 Match Negedge Detection B1 Match B1 Match Negedge Detection B1 Match Negedge Detection Output Pin EDPOL = 0 Figure 28-39.
Page 864 Enhanced Modular Input/Output Subsystem (eMIOS200) Write to A2 Cycle n Cycle n + 1 System Clock Prescaler EMIOS_CCNTR Time A1 Value 0x000004 0x000000 A2 Value 0x000000 A1 Match Negedge B1 Value 0x000008 Detection A1 Match A1 Match Posedge A1 Match Posedge Detection Detection A1 Match Negedge Detection...
Page 865 Enhanced Modular Input/Output Subsystem (eMIOS200) Cycle n Cycle n + 1 Cycle n + 2 MODE[6] = 1 Match A1 Write to A2 Write to B2 Match B1 Internal Counter Match A1 Match B1 Write to A2 Match B1 0x000008 0x000006 0x000004 0x000002...
Page 866 Enhanced Modular Input/Output Subsystem (eMIOS200) Cycle n Cycle n + 1 Cycle n + 2 MODE[6] = 1 Match A1 Write to A2 Write to B2 Match B1 Internal Counter Match A1 Match B1 Write to A2 Match B1 0x000008 0x000006 0x000004 0x000002...
Page 867 Enhanced Modular Input/Output Subsystem (eMIOS200) EMIOS_CCNTR Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Time Output Pin 100% A1 Value 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 A2 Value 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001...
Page 868 Enhanced Modular Input/Output Subsystem (eMIOS200) Cycle n Cycle n + 1 Cycle n + 2 Write to B2 Write to B2 Selected Write to A2 Write to A2 Counter Bus 0x000006 0x000005 0x000001 Time Selected Counter = 2 A1/B1 Load Signal A1 Value 0x000020 0x000015...
Page 869 Enhanced Modular Input/Output Subsystem (eMIOS200) Write to A2 Selected Write to B2 Counter Bus 0x000020 0x000015 0x000013 0x000001 Time 0x000015 0x000013 A1 Value A2 Value 0x000015 0x000013 B1 Value 0x000002 0x000004 B2 Value 0x000002 0x000004 Internal Time Base Internal Counter is Set to 1 on A1 Match 0x000004 0x000002...
Page 870 Enhanced Modular Input/Output Subsystem (eMIOS200) Write to A2 Selected Write to B2 Counter Bus 0x000020 0x000015 0x000013 0x000001 Time 0x000015 0x000013 A1 Value A2 Value 0x000015 0x000013 B1 Value 0x000002 0x000004 B2 Value 0x000002 0x000004 Internal Time Base Internal Counter is Set to 1 on A1 Match 0x000004 0x000002...
Page 871 Enhanced Modular Input/Output Subsystem (eMIOS200) The FLAG bit is not set either in case of a FORCMA or FORCMB or even if both forces are issued at the same time. NOTE FORCMA and FORCMB have the same behavior even in freeze or normal mode regarding the output pin transition.
Page 872 Enhanced Modular Input/Output Subsystem (eMIOS200) Cycle n Cycle n+ 1 Cycle n + 2 Write to B2 Selected Counter Bus 0x000020 0x000001 Time A1 Value 0x000015 0x000004 A2 Value 0x000015 0x000004 B1 Value 0x000003 B2 Value 0x000003 0x000003 0x000001 Time Dead-Time Dead-Time Dead-Time...
Page 873 Enhanced Modular Input/Output Subsystem (eMIOS200) FLAG can be generated at B1 matches, when MODE[5] is cleared, or on either A1 or B1 matches when MODE[5] is set. If subsequent matches occur on comparators A and B, the PWM pulses continue to be generated, regardless of the state of the FLAG bit.
Page 874 Enhanced Modular Input/Output Subsystem (eMIOS200) The output pin transitions are based on the negedges of the A1 and B1 match signals. Figure 28-48 shows in cycle(n + 1) the value of the A1 register being set to zero. In this case, the match posedge is used instead of the negedge to transition the output flip-flop.
Page 875 Enhanced Modular Input/Output Subsystem (eMIOS200) Cycle n Cycle n+1 Cycle n+2 MODE[6] = 1 Match A1 Write to A2 Write to B2 Match B1 Selected Match A1 Match B1 Write to A2 Match B1 Counter Bus 0x000008 0x000006 0x000004 0x000002 0x000001 Time Due to B1 Match...
Page 876 Enhanced Modular Input/Output Subsystem (eMIOS200) cycle is varied and must not create glitches. The mode is intended to be used in conjunction with other channels executing in the same mode and sharing a common timebase. It supports each channel with a fixed PWM leading edge position with respect to the other channels and the ability to generate a trigger signal at any point in the period that can be output from the module to initiate activity in other parts of the device, such as starting ADC conversions.
Page 877 Enhanced Modular Input/Output Subsystem (eMIOS200) typical setup to obtain a trigger with FLAG is enabling DMA and driving the channel’s ipd_done input high. A2 is not buffered and therefore its update is immediate. If the channel is running when a change is made this could cause either the loss of one trigger event or the generation of two trigger events within the same period.
Page 878 Enhanced Modular Input/Output Subsystem (eMIOS200) Match A1 Match B1 Match B1 Match A2 Match A2 write to A1 and B2 write to B2 Match A1 Selected Counter Bus 0x0011FF 0x001000 0x000700 0x000500 0x000400 0x000000 Time Output Flip-Flop FLAG Pin/Register 0x000400 A1 Value 0xxxxxxx 0x001000...
Page 879 Enhanced Modular Input/Output Subsystem (eMIOS200) Match A1 Match B1 Match B1 does not occur Match A2 write to A1 Match A1 Match A2 and B2 write to B2 Selected Counter Bus 0x0011FF 0x001000 0x000500 0x000400 0x000000 Time Output Flip-Flop FLAG Pin/Register 0x000400 A1 Value 0xxxxxxx...
Page 880 Enhanced Modular Input/Output Subsystem (eMIOS200) Selected Clock EMIOSI 5-bit Counter IF[3:0] = 0010 Time Filter Out Figure 28-56. Input Programmable Filter Example 28.4.1.3 Clock Prescaler (CP) The CP divides the GCP output signal to generate a clock enable for the internal counter of the unified channels.
Page 881 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.4.2 IP Bus Interface Unit (BIU) The BIU provides the interface between the internal interface bus (IIB) and the peripheral bus, allowing communication among all submodules and this IP interface. The BIU allows 8-, 16-, and 32-bit access. They are performed over a 32-bit data bus in a single cycle clock.
Page 882 Enhanced Modular Input/Output Subsystem (eMIOS200) 28.8 Initialization/Application Information On resetting the eMIOS200 all unified channels enter GPIO input mode. 28.8.1 Considerations Before changing an operating mode, the unified channel must be programmed to GPIO mode and EMIOS_CADR[n] and EMIOS_CBDR[n] registers must be updated with the correct values for the next operating mode.
Page 883 Enhanced Modular Input/Output Subsystem (eMIOS200) PRESCALED CLOCK RATIO = 1 (Bypassed) Clock Prescaled Clock = 1 See Note Internal Counter Match Value = 3 Note: When a match occurs, the first clock cycle is used to clear the internal counter, starting another period.
Page 884 Enhanced Modular Input/Output Subsystem (eMIOS200) PRESCALED CLOCK RATIO = 3 System Clock Prescaler Clock Enable Internal Counter See Note Match Value = 3 FLAG Set Event FLAG Pin/Register FLAG Clear Note: When a match occurs, the first clock cycle is used to clear the internal counter, and only after a second edge of prescaled clock the counter will start counting.
Page 885 Chapter 29 Controller Area Network (FlexCAN) 29.1 Introduction The PXN20 contains as many as six controller area network (FlexCAN) blocks. Each FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B and ISO Standard 11898. The CAN protocol is used as a serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth.
Page 886 Controller Area Network (FlexCAN) FlexCAN MB63 Message Protocol Buffer MB62 Interface Management MB61 MB60 RXIMR63 max MB # CNTXx RXIMR62 (0–63) CNRXx ID Mask Storage 256 bytes 1 KB RXIMR1 RXIMR0 Bus Interface Unit Clocks, Address and Data Buses, Slave Interface Interrupt and Test Signals Figure 29-1.
Page 887 Controller Area Network (FlexCAN) • Individual Rx mask registers per message buffer • Includes 1056 bytes of RAM used for message buffer storage • Includes 256 bytes of RAM used for individual Rx mask registers • Full featured Rx FIFO with storage capacity for six frames and internal pointer handling •...
Page 888 Controller Area Network (FlexCAN) 29.1.3.3 Listen-Only Mode In this mode, transmission is disabled, all error counters are frozen, and the module operates in a CAN error passive mode. Only messages acknowledged by another CAN station are received. If FlexCAN detects a message that has not been acknowledged, it flags a BIT0 error (without changing the REC), as if it was trying to acknowledge the message.
Page 889 Controller Area Network (FlexCAN) The offset address ranges 0x0060–0x047F and 0x0880–0x097F are occupied by two separate embedded memories. These two ranges are completely occupied by RAM (1 KB and 256 bytes, respectively) when FlexCAN is configured with 64 MBs. Furthermore, if the BCC bit in CANx_MCR is negated, then the whole Rx individual mask registers address range (0x0880–0x097F) is considered reserved space.
Page 890 Controller Area Network (FlexCAN) The FlexCAN module stores CAN messages for transmission and reception using a message buffer structure. Each MB is formed by 16 bytes mapped in memory as described in Table 29-2. The FlexCAN module can manage as many as 64 message buffers. Table 29-2 shows a standard/extended message buffer (MB0) memory map, using 16 bytes (0x80–0x8F) total space.
Page 891 Controller Area Network (FlexCAN) One of the following actions be taken to avoid the above problems: • Do not enable the RxFIFO. If CANx_MCR[FEN]=0 then the Rx FIFO is disabled and thus the masks RXGMASK, RX14MASK and RX15MASK do not affect it. •...
Page 892 Controller Area Network (FlexCAN) Table 29-3. Message Buffer Field Descriptions (continued) Name Description ID Extended Bit. This bit identifies whether the frame format is standard or extended. 0 Frame format is standard. 1 Frame format is extended. Remote Transmission Request. This bit is used for requesting transmissions of a data frame. If FlexCAN transmits this bit as 1 (recessive) and receives it as 0 (dominant), it is interpreted as arbitration loss.
Page 893 Controller Area Network (FlexCAN) Table 29-4. Message Buffer Code for Rx Buffers (continued) Rx Code before Rx Code after Description Comment Rx New Frame Rx New Frame 0110 OVERRUN: A frame was 0010 If the code indicates OVERRUN but the CPU reads overwritten into a full buffer.
Page 894 Controller Area Network (FlexCAN) data from the FIFO (the oldest frame received and not read yet). The region 0x90–0xDC is reserved for internal use of the FIFO engine. The region 0xE0–0xFC contains an eight-entry ID table that specifies filtering criteria for accepting frames into the FIFO. Figure 29-4 shows the three different formats that the elements of the ID table can assume, depending on the IDAM field of the CANx_MCR.
Page 895 Controller Area Network (FlexCAN) Table 29-6. ID Table 0–7 Field Descriptions Name Description Remote Frame. This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID. 0 Remote frames are rejected and data frames can be accepted. 1 Remote frames can be accepted and data frames are rejected.
Page 896 Controller Area Network (FlexCAN) Table 29-7. CANx_MCR Field Descriptions Field Description MDIS Module Disable. Controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the clock to the CAN protocol interface and message buffer management submodules. This is the only bit in CANx_MCR not affected by soft reset.
Page 897 Controller Area Network (FlexCAN) Table 29-7. CANx_MCR Field Descriptions (continued) Field Description SOFT_RST Soft Reset. When asserted, FlexCAN resets its internal state machines and some of the memory-mapped registers. The following registers are affected by soft reset: • CANx_MCR (except the MDIS bit) •...
Page 898 Controller Area Network (FlexCAN) Table 29-7. CANx_MCR Field Descriptions (continued) Field Description Backwards Compatibility Configuration. Provided to support backwards compatibility with previous FlexCAN versions. When this bit is negated, the following configuration is applied: • For MCUs supporting individual Rx ID masking, this feature is disabled. Instead of individual ID masking per MB, FlexCAN uses its previous masking scheme with CANx_RXGMASK, CANx_RX14MASK, and CANx_RX15MASK.
Page 899 Controller Area Network (FlexCAN) in freeze mode. Exceptions are the BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK, and BOFF_REC bits, which can be accessed at any time. Offset: Base + 0x0004 Access: User read/write PRESDIV PSEG1 PSEG2 Reset R BOFF ERR_ CLK_ TWRN RWRN BOFF TSYN LBUF LOM...
Page 900 Controller Area Network (FlexCAN) Table 29-8. CANx_CTRL Field Descriptions Bits Description CLK_SRC CAN Engine Clock Source. Selects the clock source to the CAN Protocol Interface (CPI) to be either the system clock (driven by the PLL) or the crystal oscillator clock. The selected clock is the one fed to the prescaler to generate the serial clock (SCK).
Page 901 Controller Area Network (FlexCAN) Table 29-8. CANx_CTRL Field Descriptions Bits Description Listen-Only Mode. Configures FlexCAN to operate in listen-only mode. In this mode, the FlexCAN module receives messages without giving any acknowledge. It is not possible to transmit any message in this mode. 0 FlexCAN module is in normal active operation, listen only mode is deactivated.
Page 902 Controller Area Network (FlexCAN) defined: a global mask, used for Rx buffers 0–13 and 16–63, and two extra masks dedicated for buffers 14 and 15. The meaning of each mask bit is the following: • Mask bit = 0: the corresponding incoming ID bit is “don’t care.” •...
Page 903 Controller Area Network (FlexCAN) CANx_RXGMASK also applies to all elements of the ID filter table, except elements 6-7, which have individual masks. The contents of this register must be programmed while the module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames.
Page 904 Controller Area Network (FlexCAN) • Address Offset: 0x18 • Reset Value: 0xFFFF_FFFF 29.3.4.5 Error Counter Register (CANx_ECR) CANx_ECR has two 8-bit fields reflecting the value of two FlexCAN error counters: the transmit error counter (TXECTR field) and receive error counter (RXECTR field). The rules for increasing and decreasing these counters are described in the CAN protocol and are completely implemented in the FlexCAN module.
Page 905 Controller Area Network (FlexCAN) Offset: Base + 0x001C Access: User read/write Reset RXECTR TXECTR Reset Figure 29-9. Error Counter Register (CANx_ECR) 29.3.4.6 Error and Status Register (CANx_ESR) This register reflects various error conditions, some general status of the device, and it is the source of four interrupts to the CPU.
Page 906 Controller Area Network (FlexCAN) Table 29-11. CANx_ESR Field Descriptions Field Description TWRN_INT If the WRN_EN bit in CANx_MCR is set, the TWRN_INT bit is set when the TXWRN flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If the corresponding mask bit in the CANx_CTRL register (TWRN_MSK) is set, an interrupt is generated to the CPU.
Page 907 Controller Area Network (FlexCAN) Table 29-11. CANx_ESR Field Descriptions (continued) Field Description IDLE CAN Bus IDLE State. This status bit indicates when CAN bus is in IDLE state. 0 No such occurrence. 1 CAN bus is now IDLE. TXRX Current FlexCAN Status (Transmitting/Receiving). This status bit indicates if FlexCAN is transmitting or receiving a message when the CAN bus is not in IDLE state.
Page 908 Controller Area Network (FlexCAN) Table 29-12. CANx_IMASK2 Field Descriptions Field Description BUFnM Message Buffer n Mask. Enables or disables the respective FlexCAN message buffer (MB63 to MB32) Interrupt. 0 The corresponding buffer Interrupt is disabled. 1 The corresponding buffer Interrupt is enabled. Note: Setting or clearing a bit in the CANx_IMASK2 register can assert or negate an interrupt request, respectively.
Page 909 Controller Area Network (FlexCAN) Offset: Base + 0x002C Access: User read/write R BUF Reset R BUF Reset Figure 29-13. Interrupt Flag 2 Register (CANx_IFLAG2) Table 29-14. CANx_IFLAG2 Field Descriptions Field Description BUFnI Message Buffer n Interrupt. Each bit represents the respective FlexCAN message buffer (MB63–MB32) interrupt. Write 1 to clear.
Page 910 Controller Area Network (FlexCAN) Table 29-15. CANx_IFLAG1 Field Descriptions Field Description BUF31I– Message Buffer n Interrupt. Each bit represents the respective FlexCAN message buffer (MB31 to MB8) interrupt. BUF8I Write 1 to clear. 0 No such occurrence. 1 The corresponding buffer has successfully completed transmission or reception. BUF7I Buffer MB7 Interrupt or “FIFO Overflow”...
Page 911 Controller Area Network (FlexCAN) Offset: Base + 0880 - 0x0975 Access: User read/write MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 Reset MI15 MI14 MI13 MI12 MI11 MI10 Reset Figure 29-15. Rx Individual Mask Registers (CANx_RXIMR0 – CANx_RXIMR63) Table 29-16.
Page 912 Controller Area Network (FlexCAN) 29.4.1 Transmit Process If the MB is active (transmission pending), write an ABORT code (‘1001’) to the code field of the control and status word to request an abortion of the transmission, then read back the code field and the IFLAG1/2 register to check if the transmission was aborted (see Section 29.4.5.1, Transmission Abort Mechanism).
Page 913 Controller Area Network (FlexCAN) Once the highest priority MB is selected, it is transferred to a temporary storage space called serial message buffer (SMB), which has the same structure as a normal MB but is not user accessible. This operation is called “move-out” and after it is done, write access to the corresponding MB is blocked (if the AEN bit in CANx_MCR is asserted).
Page 914 Controller Area Network (FlexCAN) executed, the MB remains locked, unless the CPU reads the C/S word of another MB. Only a single MB is locked at a time. The only mandatory CPU read operation is the one on the control and status word to assure data coherency (see Section 29.4.5, Data Coherence).
Page 915 Controller Area Network (FlexCAN) • The code field is either EMPTY or else it is FULL or OVERRUN but the CPU has already serviced the MB (read the C/S word and then unlocked the MB) If the first MB with a matching ID is not free to receive the new frame, then the matching algorithm keeps looking for another free MB until it finds one.
Page 916 Controller Area Network (FlexCAN) 29.4.5.1 Transmission Abort Mechanism The abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback mechanism is provided to inform the CPU if the transmission was aborted or if the frame could not be aborted and was transmitted instead.
Page 917 Controller Area Network (FlexCAN) The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide which MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration process, the data of that MB may no longer be coherent, therefore deactivation of that MB is done. Even with the coherence mechanism described above, writing to the control and status word of active MBs when not in freeze mode may produce undesirable results.
Page 918 Controller Area Network (FlexCAN) then. If the MB is not unlocked in time and yet another new message with the same ID arrives, then the new message overwrites the one on the SMB and there is no indication of lost messages either in the code field of the MB or in the error and status register.
Page 919 Controller Area Network (FlexCAN) The eight elements of the filter table are individually affected by the first eight individual mask registers (CANx_RXIMR0 – CANx_RXIMR7), allowing very powerful filtering criteria to be defined. The rest of the RXIMR, starting from RXIM8, continue to affect the regular MBs, starting from MB8. If the BCC bit is negated, then the FIFO filter table is affected by the legacy mask registers as follows: element 6 is affected by CANx_RX14MASK, element 7 is affected by CANx_RX15MASK and the other elements (0 to 5) are affected by CANx_RXGMASK.
Page 920 Controller Area Network (FlexCAN) 29.4.7.4 Protocol Timing The clock source to the CAN protocol interface (CPI) can be either the system clock or a direct feed from the oscillator pin EXTAL. The clock source is selected by the CLK_SRC bit in the CANx_CTRL. The clock is fed to the prescaler to generate the serial clock (SCK).
Page 921 Controller Area Network (FlexCAN) NRZ Signal Time Segment 1 Time Segment 2 SYNCSEG (PROPSEG + PSEG1 + 2) (PSEG2 + 1) 4 ... 16 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure 29-16.
Page 922 Controller Area Network (FlexCAN) Table 29-18. CAN Standard Compliant Bit Time Segment Settings (continued) Resynchronization Time Segment 1 Time Segment 2 Jump Width 8 .. 15 1 .. 4 9 .. 16 1 .. 4 29.4.7.5 Arbitration and Matching Timing During normal transmission or reception of frames, the arbitration, match, move in and move out processes are executed during certain time windows inside the CAN frame, as shown in Figure...
Page 923 Controller Area Network (FlexCAN) After requesting freeze mode, the user must wait for the FRZ_ACK bit to be asserted in CANx_MCR before executing any other action, otherwise FlexCAN can operate in an unpredictable way. In freeze mode, all memory mapped registers are accessible. Exiting freeze mode is done in one of these ways: •...
Page 924 Controller Area Network (FlexCAN) The other two interrupt sources (bus off/transmit warning/receive warning and error) generate interrupts like the MB interrupt sources, and can be read from CANx_ESR. The bus off/transmit warning/receive warning and error interrupt mask bits are located in the CANx_CTRL. 29.4.10 Bus Interface The CPU access to FlexCAN registers are subject to the following rules: •...
Page 925 Controller Area Network (FlexCAN) NOT_RDY bits in the CANx_MCR are set. The CNTX pin is in recessive state and FlexCAN does not initiate frame transmission nor receives any frames from the CAN bus. Note that the message buffer contents are not affected by reset, so they are not automatically initialized. For any configuration change/initialization, it is required that FlexCAN is put into freeze mode (see Section 29.4.8.1, Freeze Mode).
Page 926 Controller Area Network (FlexCAN) PXN20 Microcontroller Reference Manual, Rev. 1 29-42 Freescale Semiconductor...
Page 927 Chapter 30 Deserial – Serial Peripheral Interface (DSPI) 30.1 Introduction The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the PXN20 and external devices. The DSPI supports pin-count reduction through serialization and deserialization of eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol.
Page 928 Deserial – Serial Peripheral Interface (DSPI) 30.1.1 Block Diagram Figure 30-2 is a simplified block diagram of the DSPI that illustrates the functionality and interdependence of major blocks. eDMA INTC DMA and interrupt control TX FIFO RX FIFO TXSS TX data RX data Internal Parallel Inputs...
Page 929 Deserial – Serial Peripheral Interface (DSPI) — Parameterized number of transfer attribute registers (from two to eight) — Serial clock with programmable polarity and phase — Various programmable delays — Programmable serial frame size of 4 to 32 bits, expandable by software control —...
Page 930 Deserial – Serial Peripheral Interface (DSPI) 30.1.3.1 SPI Configuration The SPI configuration allows the DSPI to send and receive serial data. This configuration allows the DSPI to operate as a basic SPI block with the FIFOs providing support for external queue operation. Data to be transmitted and data received reside in separate FIFOs.
Page 931 Deserial – Serial Peripheral Interface (DSPI) 30.1.4.4 Halt Mode Halt mode is used for MCU power management and controlled by the individual HLT bits in the SIU_HLT0 register. When a request is made to enter halt mode (assert HLT bit), the DSPI block acknowledges the request and completes the transfer in progress.
Page 932 Deserial – Serial Peripheral Interface (DSPI) Table 30-2. DSPI Memory Map Offset from DSPI_BASE DSPI_A = 0xFFF9_0000 Register Access Reset Value Section/Page DSPI_B = 0xFFF9_4000 DSPI_C = 0xC3F9_0000 DSPI_D = 0xC3F9_4000 0x0000 DSPI_MCR—DSPI module configuration register 0x0000_4001 30.3.2.1/30-7 0x0004 Reserved 0x0008 DSPI_TCR—DSPI transfer count register 0x0000_0000...
Page 933 Deserial – Serial Peripheral Interface (DSPI) Table 30-2. DSPI Memory Map (continued) Offset from DSPI_BASE DSPI_A = 0xFFF9_0000 Register Access Reset Value Section/Page DSPI_B = 0xFFF9_4000 DSPI_C = 0xC3F9_0000 DSPI_D = 0xC3F9_4000 0x00D0 DSPI_DSICR1—DSPI DSI TSB configuration register 1 0x0000_0000 30.3.2.15/30-27 0x00D4–0x3FFF Reserved...
Page 934 Deserial – Serial Peripheral Interface (DSPI) Table 30-3. DSPI_MCR Field Descriptions (continued) Field Description DCONF DSPI Configuration. The DCONF field selects between the three different configurations of the DSPI. The values below list the DCONF values for the various configurations. DCONF DSPI Configuration Reserved...
Page 935 Deserial – Serial Peripheral Interface (DSPI) Table 30-3. DSPI_MCR Field Descriptions (continued) Field Description DIS_RXF Disable Receive FIFO. The DIS_RXF bit provides a mechanism to disable the RX FIFO. When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI. See Section 30.4.3.3, FIFO Disable Operation, for details.
Page 936 Deserial – Serial Peripheral Interface (DSPI) Offset: DSPI_BASE + 0x0008 Access: User read/write SPI_TCNT Reset Reset Figure 30-4. DSPI Transfer Count Register (DSPI_TCR) Table 30-4. DSPI_TCR Field Descriptions Field Description SPI_TCNT SPI Transfer Counter. SPI_TCNT is used to keep track of the number of SPI transfers made. The SPI_TCNT field counts the number of SPI transfers the DSPI makes.
Page 937 Deserial – Serial Peripheral Interface (DSPI) In continuous clock mode, only t is supported for TSB. However, in TSB noncontinuous clock mode, both the PDT and DT delays are valid. Offset: DSPI_BASE + 0x000C (DSPI_CTAR0) 0x001C (DSPI_CTAR4) Access: User 0x0010 (DSPI_CTAR1) 0x0020 (DSPI_CTAR5) read/write 0x0014 (DSPI_CTAR2)
Page 938 Deserial – Serial Peripheral Interface (DSPI) Table 30-5. DSPI_CTARn Field Description (continued) Field Description CPHA Clock Phase. The CPHA bit selects which edge of SCK causes data to change and which edge causes data to be captured. This bit is used in both master and slave mode. For successful communication between serial devices, the devices must have identical clock phase settings.
Page 939 Deserial – Serial Peripheral Interface (DSPI) Table 30-5. DSPI_CTARn Field Description (continued) Field Description Baud Rate Prescaler. The PBR field selects the prescaler value for the baud rate. This field is only used in master mode. The baud rate is the frequency of the serial communications clock (SCK). The system clock is divided by the prescaler value before the baud rate selection takes place.
Page 940 Deserial – Serial Peripheral Interface (DSPI) Table 30-6. DSPI SCK Duty Cycle CPHA SCK Duty Cycle 50/50 50/50 33/66 40/60 43/57 50/50 66/33 60/40 57/43 Table 30-7. DSPI Transfer Frame Size FMSZ Framesize FMSZ Framesize 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved...
Page 941 Deserial – Serial Peripheral Interface (DSPI) Table 30-9. DSPI After SCK Delay Scaler After SCK Delay After SCK Delay Scaler Value Scaler Value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 0100 1100 8192 0101 1101 16384 0110 1110 32768...
Page 942 Deserial – Serial Peripheral Interface (DSPI) 30.3.2.4 DSPI Status Register (DSPI_SR) The DSPI_SR contains status and flag bits. The bits reflect the status of the DSPI and indicate the occurrence of events that can generate interrupt or DMA requests. Software can clear a flag bit in the DSPI_SR by writing a 1 to it.
Page 943 Deserial – Serial Peripheral Interface (DSPI) Table 30-12. DSPI_SR Field Descriptions Field Description Transfer Complete Flag. The TCF bit indicates that all bits in a frame have been shifted out. The TCF bit is set at the end of the frame transfer. The TCF bit remains set until cleared by software. 0 Transfer not complete.
Page 944 Deserial – Serial Peripheral Interface (DSPI) 30.3.2.5 DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER) The DSPI_RSER serves two purposes. It enables flag bits in the DSPI_SR to generate DMA requests or interrupt requests. The DSPI_RSER also selects the type of request to be generated. See the individual bit descriptions for information on the types of requests the bits support.
Page 945 Deserial – Serial Peripheral Interface (DSPI) Table 30-13. DSPI_RSER Field Descriptions (continued) Field Description RFOF_RE Receive FIFO Overflow Request Enable. The RFOF_RE bit enables the RFOF flag in the DSPI_SR to generate an interrupt requests. 0 RFOF interrupt requests are disabled. 1 RFOF interrupt requests are enabled.
Page 946 Deserial – Serial Peripheral Interface (DSPI) Offset: DSPI_BASE + 0x0034 Access: User read/write CONT CTAS PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 Reset TXDATA Reset Figure 30-8. DSPI PUSH TX FIFO Register (DSPI_PUSHR) Table 30-14. DSPI_PUSHR Field Descriptions Field Description CONT Continuous Peripheral Chip Select Enable.
Page 947 Deserial – Serial Peripheral Interface (DSPI) Table 30-14. DSPI_PUSHR Field Descriptions (continued) Field Description PCSn Peripheral Chip Select 0–7. The PCS bits select which PCS signals are asserted for the transfer. 0 Negate the PCS[x] signal. 1 Assert the PCS[x] signal. TXDATA Transmit Data.
Page 948 Deserial – Serial Peripheral Interface (DSPI) Offset: DSPI_BASE+ Access: Read 0x003C (DSPI_TXFR0) 0x0040 (DSPI_TXFR1) 0x0044 (DSPI_TXFR2) 0x0048 (DSPI_TXFR3) TXCMD Reset TXDATA Reset Figure 30-10. DSPI Transmit FIFO Register 0–15 (DSPI_TXFRn) Table 30-16. DSPI_TXFRn Field Descriptions Field Description TXCMD Transmit Command. The TXCMD field contains the command that sets the transfer attributes for the SPI data. See Section 30.3.2.6, DSPI PUSH TX FIFO Register (DSPI_PUSHR), for details on the command field.
Page 949 Deserial – Serial Peripheral Interface (DSPI) Offset: DSPI_BASE+ Access: Read 0x007C (DSPI_RXFR0) 0x0080 (DSPI_RXFR1) 0x0084 (DSPI_RXFR2) 0x0088 (DSPI_RXFR3) Reset RXDATA Reset Figure 30-11. DSPI Receive FIFO Registers 0–15 (DSPI_RXFRn) Table 30-17. DSPI_RXFRn Field Description Field Description RXDATA Receive Data. The RXDATA field contains the received SPI data. 30.3.2.10 DSPI DSI Configuration Register (DSPI_DSICR) The DSI Configuration Register selects various attributes associated with DSI and CSI configurations.
Page 950 Deserial – Serial Peripheral Interface (DSPI) Table 30-18. DSPI_DSICR Field Descriptions Field Description TSBC Timed Serial Bus Configuration. The TSBC bit enables the Timed Serial Bus configuration. This configuration allows 32-bit data to be used. It also allows T to be programmable. See Section 30.4.10, Timed Serial Bus (TSB), for detailed information.
Page 951 Deserial – Serial Peripheral Interface (DSPI) The DSPI_SDR is a 32-bit register. The upper 16 bits are only used when TSB is enabled. For non-TSB configurations, only the least 16 significant bits are used. Offset: DSPI_BASE + 00C0 Access: Read SER_DATA Reset SER_DATA...
Page 952 Deserial – Serial Peripheral Interface (DSPI) Table 30-20. DSPI_ASDR Field Description Field Description ASER_DATA Alternate Serialized Data. The ASER_DATA field holds the alternate data to be serialized. 30.3.2.13 DSPI DSI Transmit Comparison Register (DSPI_COMPR) The DSPI_COMPR holds a copy of the last transmitted DSI data. The DSPI_COMPR is read-only. DSI data is transferred to this register as it is loaded into the TX Shift Register.
Page 953 Deserial – Serial Peripheral Interface (DSPI) Offset: DSPI_BASE + 0x00CC Access: Read DESER_DATA Reset DESER_DATA Reset Figure 30-16. DSPI Deserialization Data Register (DSPI_DDR) Table 30-22. DSPI_DDR Field Description Field Description DESER_DATA Deserialized Data. When TSB configuration is set, the DESER_DATA field holds deserialized data that is presented as signal states to the parallel output signals.
Page 954 Deserial – Serial Peripheral Interface (DSPI) Table 30-23. DSPI_SDR Field Descriptions Field Description TSBCNT Timed Serial Bus Operation Count. When TSBC is set, TSBCNT defines the length of the TSB frame. A number between 4 and 32. The TSBCNT field selects number of bits to be shifted out during a transfer in TSB operation. The field sets the number of SCK cycles that the bus master generates to complete the transfer.
Page 955 Deserial – Serial Peripheral Interface (DSPI) shift register of the Slave, and vice versa. At the end of a transfer, the TCF bit in the DSPI_SR is set to indicate a completed transfer. Figure 30-18 illustrates how master and slave data is exchanged. DSPI Master DSPI Slave SOUT...
Page 956 Deserial – Serial Peripheral Interface (DSPI) In SPI configuration, master mode transfer attributes are controlled by the SPI command in the current TX FIFO entry. The CTAS field in the SPI command selects which of the eight DSPI_CTARn registers are used to set the transfer attributes.
Page 957 Deserial – Serial Peripheral Interface (DSPI) 30.4.1.5 Debug Mode The debug mode is used for system development and debugging. If the MCU enters debug mode while the FRZ bit in the DSPI_MCR is set, the DSPI stops all serial transfers and enters a stopped state. If the MCU enters debug mode while the FRZ bit is negated, the DSPI behavior is unaffected and remains dictated by the module-specific mode and configuration of the DSPI.
Page 958 Deserial – Serial Peripheral Interface (DSPI) 30.4.3 Serial Peripheral Interface (SPI) Configuration The SPI configuration transfers data serially using a shift register and a selection of programmable transfer attributes. The DSPI is in SPI configuration when the DCONF field in the DSPI_MCR is 0b00. The SPI frames can be from 4 to 16 bits long.
Page 959 Deserial – Serial Peripheral Interface (DSPI) successful communication with a SPI master. The SPI slave mode transfer attributes are set in the DSPI_CTAR0. 30.4.3.3 FIFO Disable Operation The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The DSPI operates as a double-buffered simplified SPI when the FIFOs are disabled.
Page 960 Deserial – Serial Peripheral Interface (DSPI) The DSPI ignores attempts to push data to a full TX FIFO, i.e., the state of the TX FIFO is unchanged. No error condition is indicated. 30.4.3.4.2 Draining the TX FIFO The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the TX FIFO.
Page 961 Deserial – Serial Peripheral Interface (DSPI) 30.4.3.5.2 Draining the RX FIFO Host software or the eDMA controller can remove (pop) entries from the RX FIFO by reading the DSPI POP RX FIFO Register (DSPI_POPR). For more information on DSPI_POPR, refer to Section 30.3.2.7, DSPI POP RX FIFO Register (DSPI_POPR).
Page 962 Deserial – Serial Peripheral Interface (DSPI) Alternate Serialization Data Register (DSPI_ASDR) as the source of the serialized data. See Section 30.3.2.11, DSPI DSI Serialization Data Register (DSPI_SDR), Section 30.3.2.12, DSPI DSI Alternate Serialization Data Register (DSPI_ASDR), for more details. The DSPI_SDR holds the latest parallel input signal values, which are sampled at every rising edge of the system clock.
Page 963 Deserial – Serial Peripheral Interface (DSPI) Slave Bus Interface Control Logic Shift Register 0 1 • • • • • N – 1 DSI Deserialization Parallel Data Register Outputs In TSB configuration, the number of bits N = 32. For non-TSB, N = 16. Figure 30-22.
Page 964 Deserial – Serial Peripheral Interface (DSPI) commands and data from the TX FIFO. The data returned from the bus slave is either used to drive the parallel output signals or it is stored in the RX FIFO. The CSI configuration allows serialized data and configuration or diagnostic data to be transferred to a slave device using only one serial link.
Page 965 Deserial – Serial Peripheral Interface (DSPI) Slave bus interface DSI control DSI transmit TX FIFO register comparison register Transfer priority logic Clock SCKx logic Parallel DSI serialization Shift register inputs data register SOUTx (P_IN) 0 1 • • • • • 15 Control logic PCSx (SPI)
Page 966 Deserial – Serial Peripheral Interface (DSPI) 30.4.6 Buffered SPI Operation The DSPI can use a FIFO buffering mechanism to transmit and receive commands and data to and from external devices. The transmit FIFO buffers SPI commands and data to be transferred. The receive FIFO buffers incoming serial data.
Page 967 Deserial – Serial Peripheral Interface (DSPI) DSPI_CTARn[BR]) to produce SCK with the possibility of halving the scaler division. The DBR, PBR, and BR fields in the DSPI_CTARn registers select the frequency of SCK using the following formula: Eqn. 30-5 f SYS ...
Page 968 Deserial – Serial Peripheral Interface (DSPI) Table 30-28. After SCK Delay Computation Example Prescaler Scaler PASC Fsys After SCK Delay Value Value 0b01 0b0100 100 MHz 0.96 us 30.4.7.4 Delay after Transfer (t The delay after transfer is the length of time between negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame.
Page 969 Deserial – Serial Peripheral Interface (DSPI) Table 30-30. Delay after Transfer Computation Example in TSB Configuration PDT field (Tsck) 1280 1792 1536 2560 3584 1024 3072 5120 7168 2048 6144 10240 14336 4096 12288 20480 28672 8192 24576 40960 57344 16384 49152 81920...
Page 970 Deserial – Serial Peripheral Interface (DSPI) The delay between the assertion of the PCSx signals and the assertion of PCSS is selected by the PCSSCK field in the DSPI_CTARn register based on the following formula: Eqn. 30-8 tPCSSCK =  PCSSCK At the end of the transfer the delay between PCSS negation and PCSx negation is selected by the PASC field in the DSPI_CTARn register based on the following formula:...
Page 971 Deserial – Serial Peripheral Interface (DSPI) The DSPI supports four different transfer formats: • Classic SPI with CPHA = 0 • Classic SPI with CPHA = 1 • Modified transfer format with CPHA = 0 • Modified transfer format with CPHA = 1 A modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times.
Page 972 Deserial – Serial Peripheral Interface (DSPI) Master (CPHA = 0): TCF and EOQF are set and RXCTR counter is updated at next to last SCK edge of frame (edge 15) Slave (CPHA = 0): TCF is set and RXCTR counter is updated at last SCK edge of frame (edge 16) 10 11 12 13 14 (CPOL = 0)
Page 973 Deserial – Serial Peripheral Interface (DSPI) Master (CPHA = 1): TCF and EOQF are set and RXCTR counter is updated at last SCK edge of frame (edge 16) Slave (CPHA = 1): TCF is set and RXCTR counter is updated at last SCK edge of frame (edge 16) 10 11 12 13 14 15 (CPOL = 0)
Page 974 Deserial – Serial Peripheral Interface (DSPI) every odd-numbered SCK edge. The slave also places new data on the slave SOUT on every odd-numbered clock edge. The master places its second data bit on the SOUT line one system clock after odd-numbered SCK edge. The point where the master samples the slave SOUT is selected by writing to the SMPL_PT field in the DSPI_MCR.
Page 975 Deserial – Serial Peripheral Interface (DSPI) last bit on the last edge of the SCK. The master samples the last slave SOUT bit one half SCK cycle after the last edge of SCK. No clock edge is visible on the master SCK pin during the sampling of the last bit. The SCK to PCS delay must be greater or equal to half of the SCK period.
Page 976 Deserial – Serial Peripheral Interface (DSPI) CONT bit in the SPI command. Continuous selection is enabled for the DSI configuration by setting the DCONT bit in the DSPI_DSICR. The behavior of the PCS signals in the two configurations is identical, so only SPI configuration is described.
Page 977 Deserial – Serial Peripheral Interface (DSPI) Switching CTAR registers or changing which PCS signals are asserted between frames while using continuous selection can cause errors in the transfer. The PCS signal should be negated before CTAR is switched or different PCS signals are selected. 30.4.8.6 Clock Polarity Switching Between DSPI Transfers If it is desired to switch polarity between non-continuous DSPI frames, the edge generated by the change...
Page 978 Deserial – Serial Peripheral Interface (DSPI) It is recommended that the baud rate is the same for all transfers made while using the continuous SCK. Switching clock polarity between frames while using continuous SCK can cause errors in the transfer. Continuous SCK operation is not guaranteed if the DSPI is put into halt mode or module disable mode.
Page 979 Deserial – Serial Peripheral Interface (DSPI) (CPOL = 0) (CPOL = 1) Master SOUT Master SIN Transfer 1 Transfer 2 Figure 30-37. Continuous SCK Timing Diagram (CONT = 1) 30.4.10 Timed Serial Bus (TSB) The DSPI can be programmed in timed serial bus (TSB) configuration by asserting the TSBC bit in the DSPI_DSICR register.
Page 980 Deserial – Serial Peripheral Interface (DSPI) The time between the negation of the CS at the end of one frame to the assertion of CS at the next frame is defined by: T × DT / F but delayed until the next active edge of T .
Page 981 Deserial – Serial Peripheral Interface (DSPI) unchanged in this mode with respect to the other modes and remain controlled by the CSC and ASC delay fields respectively when not in continuous SCK mode. 30.4.10.2 TSB Command Frame Format In the TSB configuration a command frame is shown in Figure 30-40.
Page 982 Deserial – Serial Peripheral Interface (DSPI) Data Frame 1 Data Frame 2 Active Phase Active Phase Invalid Invalid Master SOUT Data Selection Bit = from 1 to (PDT × DT / Fsys) TSCK Data Frame = 4 to 32 bits Figure 30-41.
Page 983 Deserial – Serial Peripheral Interface (DSPI) Table 30-34. DSPI Interrupt and DMA Request Conditions (continued) Condition Flag Interrupt Attempt to transmit with an empty transmit FIFO TFUF RX FIFO is not empty RFDF Frame received while receive FIFO is full RFOF Each condition has a flag bit in the DSPI Status Register (DSPI_SR) and an Request Enable bit in the DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER).
Page 984 Deserial – Serial Peripheral Interface (DSPI) DSPI_RSER is asserted. The RFDF_DIRS bit in the DSPI_RSER selects whether a DMA request or an interrupt request is generated. 30.4.12.6 Receive FIFO Overflow Interrupt Request The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has occurred. A receive FIFO overflow request is generated when RX FIFO and shift register are full and a transfer is initiated.
Page 985 Deserial – Serial Peripheral Interface (DSPI) ipg_enable_clk is negated, the DSPI is in a dormant state, but the memory mapped registers are still accessible. Certain read or write operations have a different affect when the DSPI is in the module disable mode.
Page 986 Deserial – Serial Peripheral Interface (DSPI) 10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit. 11. Enable serial transmission and serial reception of data by clearing the EOQF bit. 30.5.2 Baud Rate Settings Table 30-35...
Page 987 Deserial – Serial Peripheral Interface (DSPI) Table 30-36. Delay Values Delay Prescaler Values 20.0 ns 60.0 ns 100.0 ns 140.0 ns 40.0 ns 120.0 ns 200.0 ns 280.0 ns 80.0 ns 240.0 ns 400.0 ns 560.0 ns 1.1 s 160.0 ns 480.0 ns 800.0 ns 1.6 s...
Page 988 Deserial – Serial Peripheral Interface (DSPI) Table 30-37. Oak Family QSPI Compatibility with the DSPI Oak Family Control Bits Corresponding DSPI_CTARn Register Configuration DSPI Corresponding Control Bits BITSE CTAS[0] DT CTAS[1] DSCK CTAS[2] DSPI_CTARn FMSZ PCSSCK CSSCK 1111 0011 0000 1111 0011 user...
Page 989 Deserial – Serial Peripheral Interface (DSPI) 30.5.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO The memory address of the first-in entry in the TX FIFO is computed by the following equation:    Eqn.
Page 990 Deserial – Serial Peripheral Interface (DSPI) PXN20 Microcontroller Reference Manual, Rev. 1 30-64 Freescale Semiconductor...
Page 991 Chapter 31 Enhanced Serial Communication Interface (eSCI) 31.1 Introduction The eSCI allows asynchronous serial communications with peripheral devices and other CPUs. The eSCI has special features that allow the eSCI to operate as a LIN bus master, complying with the LIN 1.3, 2.0, 2.1, and SAE J2602 specification.
Page 992 Enhanced Serial Communication Interface (eSCI) • 13-bit baud rate selection • Programmable frame, payload, and character format • Support of 2 stop bits in receiver path • Hardware parity generation and checking — Programmable even or odd parity • Programmable polarity of RXD pin •...
Page 993 Enhanced Serial Communication Interface (eSCI) 31.1.3 Modes of Operation The SCI module has two functional operational modes, SCI and LIN mode, and low power modes. The availability of register bits and fields depends on the selected operational mode. 31.1.3.1 SCI Mode The SCI mode is the default functional operational mode and is described in Section 31.4.5, SCI Mode.
Page 994 Enhanced Serial Communication Interface (eSCI) If the eSCI module is in SCI mode and the system stop signal is asserted and no transmission or reception is running, the eSCI module enters the halt mode. 31.1.3.4.2 Leaving Halt Mode into SCI Mode If the eSCI module is in halt mode and the system stop signal is de-asserted and the LIN bit and the MDIS bit are 0, the eSCI module enters the SCI mode.
Page 995 Enhanced Serial Communication Interface (eSCI) NOTE eSCI_G, eSCI_H, eSCI_J, eSCI_K, eSCI_L, and eSCI_M are not implemented on the PXN20. Table 31-1. eSCI Memory Map Offset from ESCI_BASE eSCI_A = 0xFFFA_0000 eSCI_B = 0xFFFA_4000 eSCI_C = 0xFFFA_8000 eSCI_D = 0xFFFA_C000 eSCI_E = 0xFFFB_0000 Reset Register Access...
Page 996 Enhanced Serial Communication Interface (eSCI) 31.3.2.1 eSCI Baud Rate Register (eSCI_BRR) This register provides the control value for the serial baud rate. The baud rate and clock generation is specified in Section 31.4.3, Baud Rate and Clock Generation. A byte write access to only the upper byte of this register (eSCI_BRR[0:7]) will not change the content of the register.
Page 997 Enhanced Serial Communication Interface (eSCI) Table 31-3. eSCI_CR1 Field Descriptions Field Description LOOPS Loop Mode Select. Together with the RSRC control bit, this control bit defines the receiver source mode. The mode coding is defined in Table 31-4 and the modes are described in Section 31.4.5.3.2, Receiver Input Mode Selection.
Page 998 Enhanced Serial Communication Interface (eSCI) Table 31-3. eSCI_CR1 Field Descriptions (continued) Field Description Receiver Wake-Up Mode. This bit controls and indicates the receiver wake-up mode, which is described in Section 31.4.5.5, Multiprocessor Communication. 0 Normal receiver operation. 1 Receiver is in wake-up mode. Note: This bit should be set in SCI mode only.
Page 999 Enhanced Serial Communication Interface (eSCI) Table 31-5. eSCI_CR2 Field Descriptions Field Description MDIS Module Disabled Mode. This bit controls the module mode of operation, which is described in Section 31.1.3, Modes of Operation. 0 Module is not in disabled mode. 1 Module is in disabled mode.
Page 1000 Enhanced Serial Communication Interface (eSCI) Table 31-5. eSCI_CR2 Field Descriptions (continued) Field Description PMSK Parity Bit Masking. This bit defines whether the received parity bit is presented in the related bit position in the SCI Data Register (eSCI_SDR). 0 The received parity bit is presented in the bit position related to the parity bit. 1 The value 0 is presented in the bit position related to the parity bit.

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