Mitsubishi MELSEC Q Series Programming Manual page 1229

Number Name Meaning
Instruction
reception
SD381
status of 2nd
module
Ethernet Instruction
instruction reception
SD382
reception status of 3rd
status module
Instruction
reception
SD383
status of 4th
module
Number of
SD393
multiple CPUs
CPU mounting
SD394
information
Multiple CPU
Multiple CPU
system
SD395
number
information
No. 1 CPU
SD396 operation
status
No. 2 CPU
SD397 operation
status
No. 3 CPU
SD398 operation
status
No. 4 CPU
SD399
operation statu
*1 Function version is B or later.
*2 The Universal model QCPU except the Q00UJCPU, Q00UCPU, and Q01UCPU.
*3 The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*4 The module whose first 5 digits of serial No. is "08032" or later.
*5 The module whose first 5 digits of serial No. is "09012" or later.
*6 The module whose first 5 digits of serial No. is "10042" or later.
*7 The Universal model QCPU except the Q00UJCPU.
Explanation
Data configuration is the same as that of the 1st module
(SD380).
Data configuration is the same as that of the 1st module
(SD380).
Data configuration is the same as that of the 1st module
(SD380).
The number of CPU modules that comprise the multiple CPU
system is stored. (1 to 3, Empty also included)
This register stores information on the CPU module types of
CPU No.1 to No.3 and whether or not the CPU modules are
mounted.
b15 b12 b11 b8 b7
to to
SD394 Empty (0)
CPU No.3
CPU module mounted or
not mounted
0: Not mounted
1: Mounted
In a multiple CPU system configuration, the CPU number of the
host CPU is stored.
CPU No. 1: 1, CPU No. 2: 2, CPU No. 3: 3, CPU No. 4: 4
The operation information of each CPU No. is stored.
(The information on the number of multiple CPUs indicated in
SD393 is stored.)
b15 b14 to b8 b7 to
Empty Classification Operation status
mounted
0: Not mounted
1: Mounted
0: Normal
1: Minor fault
2: Medium fault
3: Major fault
F : Reset
H
Set by
(When Set)
S
(Instruction
execution)
b4 b3 b0
to to
CPU No.2 CPU No.1
S
(Initial)
CPU module type
0: Programmable
controller CPU
1: Motion CPU
2: PC CPU
b4 b3 to b0
S
(END
processing
error)
0: RUN
2: STOP
3: PAUSE
4: Initial
F : Reset
H
Corres-
Corres-
ponding
ponding
ACPU
CPU
D9
QnPRH
*1
Q00/Q01
QnU
*1
Q00/Q01
New
*1
Q00/Q01
*1
Qn(H)
QnPH
QnU
*1
Q00/Q01
QnU
*1
Q00/Q01
*7
QnU
*3
QnU
App-221
8
8
8
8
A
6
7
8