Mitsubishi MELSEC Q Series Programming Manual page 1225

Number Name Meaning
SD280
Error detection
CC-Link error
status
SD281
SD286 Points
assigned to M
SD287
(for extension)
Device
assignment
SD288 Points
assigned to B
SD289
(for extension)
Explanation
This register stores error detection status in the following bit
pattern.
Information Information
of 3) of 2)
b15 to b12 b11 to b8 b7 to
Empty
1): When Xn0 of a mounted CC-Link module turns on, the
corresponding bit is set to 1 (on).
2): When either Xn1 or XnF of a mounted CC-Link module turns
off, the corresponding bit is set to 1 (on).
3) When a mounted CC-Link module is not able to
communicate with the CPU module, the corresponding bit is
set to 1 (on).
The above modules are numbered in order of the head I/O
numbers. (However, the one where parameter setting has not
been made is not counted.)
This register stores error detection status in the following bit
pattern.
Information Information
of 3) of 2)
b15 b12 b11 b8 b7
to to to
Empty
1): When Xn0 of a mounted CC-Link module turns on, the
corresponding bit is set to 1 (on).
2): When either Xn1 or XnF of the mounted CC-Link module
turns off, the corresponding bit is set to 1 (on).
3): When a mounted CC-Link module is not able to
communicate with the CPU module, the corresponding bit is
set to 1 (on).
The above modules are numbered in order of the head I/O
numbers. (However, the one where parameter setting has not
been made is not counted.)
• The number of points assigned to M is stored with 32 bits.
• The number of 32k or less points can be assigned to M.
• The number of points assigned to B is stored with 32 bits.
• The number of 32k or less points can be assigned to B.
Set by
(When Set)
Information
of 1)
b4 b3 to b0
1st
module
2nd
module
3rd
module
4th
module
S
(Error)
Information
of 1)
b4 b3 b0
to
5st
module
6nd
module
7rd
module
8th
module
S
(Initial)
Corres-
Corres-
ponding
ponding
ACPU
CPU
D9
Qn(H)
QnPH
QnPRH
New
*4
Qn(H)
*4
QnPH
*5
QnPRH
*6
QnU
LCPU
App-217
8
8
8
8
A
6
7
8