Mitsubishi MELSEC Q Series Programming Manual page 1249

Number Name Meaning
Maximum
number of
blocks used for
the multiple
CPU high-
SD796 speed
transmission
dedicated
instruction
setting (for CPU
No.1)
Maximum
number of
blocks used for
the multiple
CPU high-
SD797 speed
transmission
Maximum number
dedicated
of blocks range
instruction
for dedicated
setting (for CPU
instructions
No.2)
Range: 1 to 7
(Default: 2 Or
Maximum
when setting
number of
other than 1 to 7,
blocks used for
the register
the multiple
operates as 7).
CPU high-
SD798 speed
transmission
dedicated
instruction
setting (for CPU
No.3)
Maximum
number of
blocks used for
the multiple
CPU high-
SD799 speed
transmission
dedicated
instruction
setting (for CPU
No.4)
*1 Function version is B or later.
*2 The module whose first 5 digits of serial No. is "04012" or later.
*3 The module whose first 5 digits of serial No. is "07032" or later.
*4 The module whose first 5 digits of serial No. is "09012" or later.
*5 The Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
*6 The range is from 1 to 9 for the Q03UDCPU, Q04UDCPU, and Q06UDHCP whose first 5 digits of serial number is
"10012" or earlier.
(Default: 2 Or when setting other than 1 to 9, the register operates as 9).
Explanation
Specifies the maximum number of blocks used for the multiple
CPU high-speed transmission dedicated instruction (target
CPU=CPU No.1). When the multiple CPU high-speed
transmission dedicated instruction is executed to the CPU No.1,
and the number of empty blocks of the dedicated instruction
transmission area is less than the setting value of this register,
SM796 is turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Specifies the maximum number of blocks used for the multiple
CPU high-speed transmission dedicated instruction (target
CPU=CPU No.2). When the multiple CPU high-speed
transmission dedicated instruction is executed to the CPU No.2,
and the number of empty blocks of the dedicated instruction
transmission area is less than the setting value of this register,
SM797 is turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Specifies the maximum number of blocks used for the multiple
CPU high-speed transmission dedicated instruction (target
CPU=CPU No.3). When the multiple CPU high-speed
*6
transmission dedicated instruction is executed to the CPU No.3,
and the number of empty blocks of the dedicated instruction
transmission area is less than the setting value of this register,
SM798 is turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Specifies the maximum number of blocks used for the multiple
CPU high-speed transmission dedicated instruction (target
CPU=CPU No.4). When the multiple CPU high-speed
transmission dedicated instruction is executed to the CPU No.4,
and the number of empty blocks of the dedicated instruction
transmission area is less than the setting value of this register,
SM799 is turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Corres-
Set by Corres-
ponding
(When ponding
ACPU
Set) CPU
D9
U
*5
(At 1 scan New
QnU
after RUN)
App-241
8
8
8
8
A
6
7
8