Omron CP1L-EL20DR-D Operation Manual page 819

PLC Setup
Name
2 2-5 Serial Gateway
2-5-1 Baud
2-5-2 Format
(data
length,
stop bits,
parity)
2-5-3 Response
Timeout
2-6 PC Link (Slave)
2-6-1 Baud
2-6-2 PC Link
Unit No.
Default Settings
9,600 bps 300 bps
600 bps
1,200 bps
2,400 bps
4,800 bps
9,600 bps
19,200 bps
38,400 bps
57,600 bps
115,200 bps
7,2,E: 7-bit 7,2,E: 7-bit data, 2 stop
data, 2 stop bits, even parity
bits, even parity
7,2,O: 7-bit data, 2 stop
bits, odd parity
7,2,N: 7-bit data, 2 stop
bits, no parity
7,1,E: 7-bit data, 2 stop
bits, even parity
7,1,O: 7-bit data, 1 stop
bit, odd parity
7,1,N: 7-bit data, 1 stop
bit, no parity
8,2,E: 8-bit data, 2 stop
bits, even parity
8,2,O: 8-bit data, 2 stop
bits, odd parity
8,2,N: 8-bit data, 2 stop
bits, no parity
8,1,E: 8-bit data, 1 stop
bit, even parity
8,1,O: 8-bit data, 1 stop
bit, odd parity
8,1,N: 8-bit data, 1 stop
bit, no parity
50: 50 × 100 ms = 5 s
50:
50 × 100 ms =
1: 1 × 100 ms
5 s
:
255: 255 × 100 ms
9,600 bps 38,400 (standard)
(disabled)
115,200 (high speed)
0 0
:
7
When setting is read Internal
by CPU Unit address
Every cycle 145
(CP1L
EM-type
CPU Unit)
161
(CP1L EL-
type CPU
Unit)
Every cycle 144
(CP1L
EM-type
CPU Unit)
160
(CP1L EL-
type CPU
Unit)
Every cycle 151
(CP1L
EM-type
CPU Unit)
167
(CP1L EL-
type CPU
Unit)
Every cycle 145
(CP1L
EM-type
CPU Unit)
161
(CP1L EL-
type CPU
Unit)
Every cycle 151
(CP1L
EM-type
CPU Unit)
167
(CP1L EL-
type CPU
Unit)
Appendix G
Bits Settings
00 to 01 hex
07
02 hex
03 hex
04 hex
05 hex
00 or
06 hex
07 hex
08 hex
09 hex
0A hex
00 to 0 hex
03
1 hex
2 hex
4 hex
5 hex
6 hex
8 hex
9 hex
A hex
C hex
D hex
E hex
08 to 00 hex
15
01 hex
:
FF hex
00 to 00 hex
07
0A hex
00 to 0 hex
03
:
7 hex
785