Omron CP1L-EL20DR-D Operation Manual page 736

Auxiliary Area Allocations by Address
Address Name
Words Bits
A215 00 to 07 First Cycle
Flags after
Network Com-
munications
Error
A216 All Network Com-
to munications
A217 Completion
Code Storage
Address
A218 All Used Commu-
nications Port
Numbers
A219 00 to 07 Communica-
tions Port
Error Flags
A262 All Maximum
and Cycle Time
A263
A264 All Present Cycle
and Time
A265
A270 All High-speed
to Counter 0 PV
A271
A272 All High-speed
to Counter 1 PV
A273
702
Function
Each flag will turn ON for just one
cycle after a communications error
occurs. Bits 00 to 07 correspond to
ports 0 to 7. Use the Used Communi-
cations Port Number stored in A218
to determine which flag to access.
Determine the cause of the error
according to the Communications
Port Completion Codes stored in
A203 to A210.
Note These flags are not effective
until the next cycle after the
communications instruction is
executed. Delay accessing
them for at least one cycle.
The completion code for a communi-
cations instruction is automatically
stored at the address with the I/O
memory address given in these
words.
Place this address into an index reg-
ister and use indirect addressing
through the index register to read the
communications completion code.
Stores the communications port
numbers used when a communica-
tions instruction is executed using
automatic communication port allo-
cations.
ON when an error occurred during
execution of a network instruction
(SEND, RECV, CMND, or PMCR).
Bits 00 to 07 correspond to commu-
nications ports 0 to 7.
These words contain the maximum
cycle time since the start of PLC
operation. The cycle time is recorded
in 8-digit hexadecimal with the left-
most 4 digits in A263 and the right-
most 4 digits in A262.
These words contain the present
cycle time in 8-digit hexadecimal with
the leftmost 4 digits in A265 and the
rightmost 4 digits in A264.
Contains the PV of high-speed
counter 0. A271 contains the left-
most 4 digits and A270 contains the
rightmost 4 digits.
The PV is cleared when operation
starts.
Contains the PV of high-speed
counter 1. A273 contains the left-
most 4 digits and A272 contains the
rightmost 4 digits.
The PV is cleared when operation
starts.
Settings Status Status
after at star-
mode
change
ON: First --- ---
cycle after
communica-
tions error
only
OFF: Other
status
I/O memory --- ---
address for
the network
communica-
tions comple-
tion code
storage
0000 to 0007 --- ---
hex: Commu-
nications port
0 to 7
ON: Error Retained ---
occurred
OFF: Normal
condition
0 to --- ---
FFFFFFFF:
0 to
429,496,729.
5 ms
(0.1-ms units)
0 to --- ---
FFFFFFFF:
0 to
429,496,729.
5 ms
--- --- Cleared
--- --- Cleared
Appendix D
Write Related
timing flags, set-
tup tings
--- ---
--- ---
--- ---
--- ---
--- ---
--- ---
Refreshed ---
each cycle
during
oversee
process.
Refreshed
when
PRV(881)
instruction
is exe-
cuted.
Refreshed ---
each cycle
during
oversee
process.
Refreshed
when
PRV(881)
instruction
is exe-
cuted.