Omron CP1L-EL20DR-D Operation Manual page 165

Sysmac cp series cp1l-el/em cpu unit
Table of Contents

Advertisement

Index Registers
,IR2
,IR1+
ON
Repeat execution of TIM instructions 100 times while incrementing each value for IR0
(timer number, PV), IR1 (Completion Flag), IR2 (W0.00 on), and @D0, and start T0 to T99.
MOVRW
The PLC memory address for the
PV area for TO is set in IR0.
T0
IR0
MOVR
The PLC memory address for the
Completion Flag for TO is set in IR1.
T0
IR1
MOVR
The PLC memory address for W0.00
is set in IR2.
W0.00
IR2
MOV
The value &100 (100 decimal) is
set in D0.
&100
D0
If the above are not set, the FOR to
JMP
NEXT loop is not executed, and if
&1
the above are set, the loop is executed.
FOR
Start of repetition (100 times)
&100
When indirect addressing for IR2
TIM
is OFF, timers are started with indirect
addressing (auto-increment) for IR0 as
,IR0+
the timer number and indirect addressing
@D0
for D0 as the timer SV.
,IR2+
Indirect addressing for IR2 will turn ON
(auto-increment) when indirect addressing
for IR1 is ON (auto-increment).
++
D0 is incremented.
D0
NEXT
Return to FOR and repeat.
JME
&1
Section 4-11
W0.00
TIM
T0000
W0.01
TIM
T0001
W6.03
TIM
T0099
0000
D100
W0.00
0001
D101
W0.01
0099
D199
W6.03
131

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents