Siemens siprotec 7SA6 User Manual page 325

Distance protection

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Definite Time

Inverse Time

C53000-G1176-C133-1

7104 >BLOCK O/C I>>

7110 >O/C InstTRIP

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Logic diagram of the I>>–stage

The logic of the overcurrent stage I> is the same as that of the I>>–stage. All

references to Iph>> must simply be replaced by ,SK! and 3I0>> by ,!. In all other

respects Figure 6-83 applies.

The logic of the inverse overcurrent stage also in principal functions the same as the

remaining stages. The time delay in this case however results from the nature of the

set characteristic (parameter ,(& &XUYH), the magnitude of the current and the time

multiplier (Figure 6-84). A pre-selection of the available characteristics was already

done during the configuration of the protection functions. Furthermore, an additional

constant time delay 7 ,S $GG (address ) may be selected, which are added to

the current dependant time derived from the IDMT characteristic. The available

characteristics are shown in the technical data, Section 10.5, Figure 10-1 to 10-3.

Figure 6-84 shows the logic diagram. The setting parameter addresses of the IEC

characteristics are shown by way of an example. In the setting information (Sub-

section 6.9.2) the different setting addresses are elaborated upon.

I>> Pickup L1

I>> Pickup L2

I>> Pickup L3

I>> Pickup E

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