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Chapter 7:
Configuration Details
Table 7-10: Configuration Options Register Description (Continued)
Bitstream Composition
Configuration can begin after the device is powered and initialization has finished, as
indicated by the INIT pin being released. After initialization, the packet processor ignores
all data presented on the configuration interface until it receives the synchronization word.
After synchronization, the packet processor waits for a valid packet header to begin the
configuration process.
Default Initial Configuration Process
Initial configuration using a default bitstream (a bitstream generated using the default
BitGen settings) begins by pulsing the PROGRAM_B pin for SelectMAP and Serial
configuration modes or by issuing the JPROG_B instruction for JTAG configuration mode.
Configuration proceeds as shown in
96
Name
GTS_CYCLE
GWE_CYCLE
Table 7-11: Configuration Sequence
Configuration
Data (hex)
FFFFFFFF
AA995566
30008001
00000007
20000000
20000000
30012001
XXXXXXXX
30018001
0167C093
30008001
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Bit Index
Startup cycle to deassert the Global Three-State
(GTS) signal.
001: Startup cycle 2
5:3
010: Startup cycle 3
011: Startup cycle 4
100: Startup cycle 5
101: Startup cycle 6
Startup phase to deassert the Global Write Enable
(GWE) signal.
001: Startup cycle 2
2:0
010: Startup cycle 3
011: Startup cycle 4
100: Startup cycle 5
101: Startup cycle 6
Table
7-11:
Explanation
Dummy word
Sync word
Type 1 write 1 words to CMD
RCRC command
NO-OP
Type 1 write 1 words to COR
Data word 0
Type 1 write 1 words to ID
Device_ID
Type 1 write 1 words to CMD
Virtex-4 FPGA Configuration User Guide
Description
UG071 (v1.12) June 2, 2017
R
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