Chapter 1: Configuration Overview; Introduction - Xilinx Virtex-4 Configuration User Manual

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Configuration Overview

Introduction

Virtex®-4 devices are configured by loading application-specific configuration data—the
bitstream—into internal memory. Because Xilinx® FPGA configuration memory is
volatile, it must be configured each time it is powered-up. The bitstream is loaded into the
device through special configuration pins. These configuration pins serve as the interface
for a number of different configuration modes:
•
•
•
•
In addition, the bitstream can be loaded through the JTAG interface:
•
The configuration modes are explained in detail in
selected by setting the appropriate level on the dedicated MODE input pins.
the Virtex-4 configuration modes.
Table 1-1: Virtex-4 Configuration Modes
Notes:
1. JTAG configuration uses the JTAG TCK pin instead of the configuration clock (CCLK).
2. I/O pre-configuration pull-up resistors are disabled with the HSWAPEN pin.
3. In SelectMAP32 D0:D31 data bits are not swapped. D0 is the LSB. D31 is the MSB.
4. If the pins are left unconnected a weak pull-up resistor on the mode pins makes slave serial the default
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Master-serial configuration mode
Slave-serial configuration mode
Master SelectMAP (parallel) configuration mode
Slave SelectMAP (parallel) configuration mode
JTAG/Boundary-Scan configuration mode
Configuration Mode
Master Serial
Slave Serial
Master SelectMAP
Slave SelectMAP8
Slave SelectMAP32 (3)
JTAG/Boundary-Scan only
mode.
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Chapter 2
M2 M1 M0
0 0 0
1 1 1
0 1 1
1 1 0
0 0 1
(1)
1 0 1
Chapter 1
The configuration mode is
Table 1-1
Data Width CCLK Direction
1 bit Output
1 bit Input
8 bits Output
8 bits Input
32 bits Input
1 bit –
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