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Revision History
The following table shows the revision history for this document.
Version
08/02/04
1.0
09/10/04
1.1
08/08/05
1.2
08/16/05
1.3
Virtex-4 FPGA Configuration User Guide
Initial Xilinx release. Printed Handbook version.
Chapters 11, 12, and 13 in the printed handbook are now Chapters 1, 2, and 3 in this
guide. Chapter 14 in the printed handbook is now Chapter 6 in this guide. There are now
eight chapters in this guide.
System Monitor functions are not supported in Virtex-4 devices, removed references.
General typographical edits for correctness and clarity. Edited
Figure
1-11,
Table
2-4, and
Removed the Virtex-4 bitstream length tables in favor of the exact numbers reported in
the ISE BitGen tool. Edited
consolidate data in the
Virtex-4 FPGA Data
Dynamic Reconfiguration Timing table to consolidate data in the
Data
Sheet.
Due to a documentation error, all configuration I/O notations have been changed from
LVTTL to LVCMOS.
www.xilinx.com
R
Revision
Figure 2-11
to add information on Slave SelectMAP32 mode.
Table 1-3
and removed the Power-Up Timing table to
Sheet. Edited
Table
1-1,
Table
1-4,
Figure
1-11. Removed the
Virtex-4 FPGA
UG071 (v1.12) June 2, 2017
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