Mpic Memory Base Register - Motorola MVME2400 Series Programmer's Reference Manual

MPIC Memory Base Register

Offset $14
Bit 3 3 2 2 2 2
1 0 9 8 7 6
Name MMBAR
BASE
Operation R/W
Reset $0000
The MPIC Memory Base Address Register (MMBAR) controls the
mapping of the MPIC control registers in PCI memory space.
IO/MEM (IO Space Indicator) This bit is hard-wired to a logic zero
to indicate PCI memory space.
MTYPx (Memory Type) These bits are hard-wired to zero to indicate
that the MPIC registers can be located anywhere in the 32-bit address
space
PRE (Prefetch) This bit is hard-wired to zero to indicate that the
MPIC registers are not prefetchable.
BASE (Base Address) These bits define the memory space base
address of the MPIC control registers. The MBASE decoder is
disabled when the BASE value is zero.
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2 2 2 2 2 2 1 1 1 1 1
5 4 3 2 1 0 9 8 7 6 5
R
$0000
1 1 1 1 1
4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Registers
2
2-97