Responding To Address Transfers - Motorola MVME2400 Series Programmer's Reference Manual

System Memory Controller (SMC)
Note
3
Table 3-5. PPC60 x Bus to ROM/Flash Access Timing (30ns @ 100 MHz)
ACCESS TYPE
4-Beat Read
4-Beat Write
1-Beat Read (1 byte)
1-Beat Read (2 to 8 bytes)
1-Beat Write
Note
PPC60 x Bus Interface
The SMC has a PowerPC slave interface only. It has no PowerPC master
interface. The slave interface is the mechanism for all accesses to
SDRAM, ROM/Flash, and the internal and external register sets.

Responding to Address Transfers

When the SMC detects an address transfer that it is to respond to, it asserts
AACK_ immediately if there is no uncompleted PPC60x bus data transfer
in process. If there is one in process, then the SMC waits and asserts
AACK_ coincident with the uncompleted data transfer's last data beat if
the SMC is the slave for the previous data. If it is not, it holds off AACK_
until the CLK after the previous data transfer's last data beat.
3-12
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The information in Table 3-4 applies to access timing when
configured for devices with an access time equal to 5 clock
periods.
CLOCK PERIODS REQUIRED FOR:
1st Beat 2nd Beat
16 64 16 64
Bits Bits Bits Bits
34 13 28 7
N/A
13 13 - -
34 13 - -
21 21 - -
The information in Table 3-5 applies to access timing when
configured for devices with an access time equal to 3 clock
periods.
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3rd Beat 4th Beat
16 64 16 64
Bits Bits Bits Bits
28 7 28 7
- - - -
- - - -
- - - -
Total
Clocks
16 64
Bits Bits
118 34
N/A
13 13
34 13
21 21