Ppc Error Test/Error Enable Register - Motorola MVME2400 Series Programmer's Reference Manual

PPC Error Test/Error Enable Register

The Error Test Register (ETEST) provides a way to inject certain types of
errors to test the PHB error capture and status circuitry. The bits within the
ETEST are defined as follows:
Address $FEFF0020
Bit
Name ETEST
Operation
Reset
DPEx (Data Parity Error Enable) These bits are used for test reasons
to purposely inject data parity errors whenever the PHB is sourcing
PPC data. A data parity error will be created on the correcponding PPC
data parity bus if a bit is set. For example, setting DPE0 will cause DP0
to be generated incorrectly. If the bit is cleared, the PHB will generate
correct data parity.
APEx (Address Parity Error Enable) These bits are used for test
reasons to purposely inject address parity errors whenever the PHB is
acting as a PPC bus master. An address parity error will be created on
the corresponding PPC address parity bus if a bit is set. For example,
setting APE0 will cause AP0 to be generated incorrectly. If the bit is
cleared, the PHB will generate correct address parity.
The Error Enable Register (EENAB) controls how the PHB is to respond
to the detection of various errors. In particular, each error type can
uniquely be programmed to generate a machine check, generate an
interrupt, generate both, or generate neither. The bits within the ETEST are
defined as follows:
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EENAB
Registers
2
2-77