Phb Hardware Configuration; Table 2-15. Phb Hardware Configuration - Motorola MVME2400 Series Programmer's Reference Manual

Write posted transactions originated from the PPC60x bus are
flushed in the following manner. The PPC Slave will set a signal
called 'xs_fbrabt' anytime it has committed to performing a posted
write transaction. This signal will remain asserted until the PCI
bound FIFO count has reached zero.
The PCI Slave decode logic settles out several clocks after the assertion of
FRAME_, at which time the PCI Slave can determine the transaction type.
If it is a read and PFBR is enabled, the PCI Slave will look at the
'xs_fbrabt' signal. If this signal is active, the PCI Slave will retry the PCI
Master.

PHB Hardware Configuration

Hawk has the ability to perform custom hardware configuration to
accommodate different system requirements. The PHB has several
functions that may be optionally enabled or disabled using passive
hardware external to Hawk. The selection process occurs at the first rising
edge of CLK after RST_ has been released. All of the sampled pins are
cascaded with several layers of registers to eliminate problems with hold
time. The following table summarizes the hardware configuration options
that relate to the PHB.

Table 2-15. PHB Hardware Configuration

Function
PCI 64-bit Enable
PPC Register Base
MPIC Interrupt Type
PPC Arbiter Mode
PCI Arbiter Mode
http://www.motorola.com/computer/literature
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
Sample Pin(s) Sampled
State
REQ64_ 0
1
RD[5] 0
1
RD[7] 0
1
RD[8] 0
1
RD[9] 0
1
Functional Description
Meaning
64-bit PCI Bus
32-bit PCI Bus
Register Base = $FEFF0000
Register Base = $FEFE0000
Parallel Interrupts
Serial Interrupts
Disabled
Enabled
Disabled
Enabled
2
2-49