Watchdog Timers - Motorola MVME2400 Series Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
Each ESTAT error bit may be programmed to generate a machine check
and/or a standard interrupt. The error response is programmed through the
PPC Error Enable Register (EENAB) on a source by source basis. When a
machine check is enabled, either the XID field in the EATTR Register or
the DFLT bit in the EENAB Register determine the master to which the
machine check is directed. For errors in which the master who originated
the transaction can be determined, the XID field is used. For errors not
associated with a particular PPC master, or associated with masters other
than processor 0,1 or 2, the DFLT bit is used. One example of an error
condition which cannot be associated with a particular PPC master would
be a PCI system error.

Watchdog Timers

PHB features two watchdog timers called Watchdog Timer 1 (WDT1) and
Watchdog Timer 2 (WDT2). Although both timers are functionally
equivalent, each timer operates completely independent of each other.
WDT1 and WDT2 are initialized at reset to a count value of 8 seconds and
16 seconds respectively. The timers are designed to be reloaded by
software at any time. When not being loaded, the timer will continuously
decrement itself until either reloaded by software or a count of zero is
reached. If a timer reaches a count of zero, an output signal will be asserted
and the count will remain at zero until reloaded by software or PHB reset
is asserted. External logic can use the output signals of the timers to
generate interrupts, machine checks, etc.
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Error Status Error Address and Attributes
XBTO
XDPE
PRTA
PSMA
PPER
PSER
From PPC bus
From PPC bus
From PCI bus
From PCI bus
Invalid
Invalid
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