I2C Interface - Motorola MVME2400 Series Programmer's Reference Manual

Table 3-8. PPC60 x to ROM/Flash (64 Bit Width) Address Mapping
PPC60x A0-A31
$X3FFFFF2
$X3FFFFF3
$X3FFFFF4
$X3FFFFF5
$X3FFFFF6
$X3FFFFF7
$X3FFFFF8
$X3FFFFF9
$X3FFFFFA
$X3FFFFFB
$X3FFFFFC
$X3FFFFFD
$X3FFFFFE
$X3FFFFFF

I2C Interface

The ASIC has an I
bus: Serial Clock Line (SCL) and Serial Data Line (SDA). This interface
has master-only capability and may be used to communicate the
configuration information to a slave I
2
The I C interface is compatible with these devices, and the inclusion of a
serial EEPROM in the memory subsystem may be desirable. The
EEPROM could maintain the configuration information related to the
memory subsystem even when the power is removed from the system.
Each slave device connected to the I
unique address. The number of interfaces connected to the I
dependent on the bus capacitance limit of 400pF.
2
For I C bus programming, the ASIC is the only master on the bus and the
serial EEPROM devices are all slaves. The I
addressing mode and transmits data one byte at a time in a serial fashion
http://www.motorola.com/computer/literature
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
ROM/Flash A22-A0
$7FFFFE
$7FFFFE
$7FFFFE
$7FFFFE
$7FFFFE
$7FFFFE
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
$7FFFFF
2
C (Inter-Integrated Circuit) two-wire serial interface
2
C device such as serial EEPROM.
2
C bus is software addressable by a
Functional Description
ROM/Flash Device Selected
Upper
Upper
Lower
Lower
Lower
Lower
Upper
Upper
Upper
Upper
Lower
Lower
Lower
Lower
2
C bus is solely
2
C bus supports 7-bit
3
3-21