Motorola MVME2400 Series Programmer's Reference Manual page 86

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Table 2-8. PCI Master Command Codes (Continued)
2
Entity Addressed
CONADD/CONDAT
CONADD/CONDAT
PPC Mapped PCI
Space
Addressing
The PCI Master generates all memory transactions using the Linear
Incrementing addressing mode.
Combining, Merging, and Collapsing
The PCI Master does not participate in any of these protocols.
Master Initiated Termination
The PCI Master can handle any defined method of target retry, target
disconnect, or target abort. If the target responds with a retry, the PCI
Master waits for the required two clock periods and attempts the
transaction again. This process continues indefinitely until the transaction
is completed, the transaction is aborted by the target, or if the transaction
is aborted due to a PHB detected bridge lock. The same happens if the
target responds with a disconnect and there is still data to be transferred.
If the PCI Master detects a target abort during a read, any untransferred
read data is filled with ones. If the PCI Master detects a target abort during
a write, any untransferred portions of data will be dropped. The same rule
applies if the PCI Master generates a Master Abort cycle.
2-28
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PPC TBST*
Transfer Type
-- Unsupported --
-- Unsupported --
Read x
Write x
-- Unsupported --
-- Unsupported --
Read 0
-- Unsupported --
MEM C/BE PCI Command
1000 Reserved
1001 Reserved
x 1010 Configuration Read
x 1011 Configuration Write
1100 Memory Read Multiple
1101 Dual Address Cycle
1 1110 Memory Read Line
1111 Memory Write and
Invalidate
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