Data Parity Error Lower Data Register; I2C Clock Prescaler Register - Motorola MVME2400 Series Programmer's Reference Manual

Data Parity Error Lower Data Register

Address
$FEF80080
Bit
Name
DPE_DL
Operation
READ ONLY
Reset
0 PL
DPE_DL DPE_DL is the value on the lower half of the PPC60x data
bus at the time of the last logging of a PPC60x data bus parity error by
the Hawk. It is updated only when dpelog goes from 0 to 1.

I2C Clock Prescaler Register

Address
$FEF80090
Bit
Name
Operation
READ ZERO
Reset
X
I2_PRESCALE_VAL I2_PRESCALE_VAL is a 16-bit register
value that will be used in the following formula for calculating
frequency of the I
2
I C CLOCK = SYSTEM CLOCK/ (I2_PRESCALE_VAL +1)/2
After power-up, I2_PRESCALE_VAL is initialized to $1F3 which
produces a 100KHz I
system clock. Writes to this register will be restricted to 4-bytes only.
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I2_PRESCALE_VAL
READ ZERO READ/WRITE
X $01F3 P
2
C gated clock signal:
2
C gated clock signal based on a 100.0MHz
Programming Model
3-61
3