Motorola MVME2400 Series Manuals

Manuals and User Guides for Motorola MVME2400 Series. We have 1 Motorola MVME2400 Series manual available for free PDF download: Programmer's Reference Manual

Motorola MVME2400 Series Programmer's Reference Manual

Motorola MVME2400 Series Programmer's Reference Manual (331 pages)

VME Processor Module  
Brand: Motorola | Category: Processor | Size: 1.33 MB
Table of contents
Safety Summary4................................................................................................................................................................
Table Of Contents8................................................................................................................................................................
About This Manual20................................................................................................................................................................
Summary Of Changes20................................................................................................................................................................
Conventions Used In This Manual24................................................................................................................................................................
Introduction25................................................................................................................................................................
Feature Summary26................................................................................................................................................................
System Block Diagram27................................................................................................................................................................
Functional Description29................................................................................................................................................................
Programming Model30................................................................................................................................................................
Pci Memory Maps36................................................................................................................................................................
Vmebus Mapping42................................................................................................................................................................
Figure 1-2. Vmebus Master Mapping43................................................................................................................................................................
Figure 1-3. Vmebus Slave Mapping45................................................................................................................................................................
System Configuration Information47................................................................................................................................................................
Isa Local Resource Bus49................................................................................................................................................................
General-purpose Software-readable Header (srh) Switch (s3)50................................................................................................................................................................
Vme Registers51................................................................................................................................................................
Lm/sig Control Register52................................................................................................................................................................
Lm/sig Status Register53................................................................................................................................................................
Location Monitor Upper Base Address Register54................................................................................................................................................................
Location Monitor Lower Base Address Register55................................................................................................................................................................
Semaphore Register 256................................................................................................................................................................
Z8536 Cio Port Pins57................................................................................................................................................................
Block Diagram61................................................................................................................................................................
Architectural Overview62................................................................................................................................................................
Ppc Bus Interface63................................................................................................................................................................
Pci Bus Interface77................................................................................................................................................................
Endian Conversion96................................................................................................................................................................
Error Handling99................................................................................................................................................................
Watchdog Timers100................................................................................................................................................................
Pci/ppc Contention Handling102................................................................................................................................................................
Transaction Ordering105................................................................................................................................................................
Phb Hardware Configuration107................................................................................................................................................................
Multi-processor Interrupt Controller (mpic) Functional Description108................................................................................................................................................................
Mpic Features108................................................................................................................................................................
External Interrupt Interface109................................................................................................................................................................
Interrupt Source Priority110................................................................................................................................................................
Csr's Readability110................................................................................................................................................................
Nesting Of Interrupt Events111................................................................................................................................................................
Spurious Vector Generation111................................................................................................................................................................
Processor's Current Task Priority111................................................................................................................................................................
Interprocessor Interrupts (ipi)111................................................................................................................................................................
Phb Detected Errors112................................................................................................................................................................
Interrupt Delivery Modes113................................................................................................................................................................
Block Diagram Description114................................................................................................................................................................
Programming Notes119................................................................................................................................................................
Architectural Notes122................................................................................................................................................................
Effects Of Interrupt Serialization123................................................................................................................................................................
Ppc Registers124................................................................................................................................................................
Pci Registers149................................................................................................................................................................
Mpic Registers162................................................................................................................................................................
System Memory Controller181................................................................................................................................................................
Bit Ordering Convention181................................................................................................................................................................
Block Diagrams182................................................................................................................................................................
Figure 3-2. Hawk's System Memory Controller Internal Data Paths184................................................................................................................................................................
Figure 3-3. Overall Sdram Connections (4 Blocks Using Register Buffers)185................................................................................................................................................................
Rom/flash Interface197................................................................................................................................................................
I2c Interface201................................................................................................................................................................
Figure 3-6. Programming Sequence For I2c Random Read206................................................................................................................................................................
Figure 3-7. Programming Sequence For I2c Current Address Read208................................................................................................................................................................
Figure 3-8. Programming Sequence For I2c Page Write210................................................................................................................................................................
Figure 3-9. Programming Sequence For I2c Sequential Read213................................................................................................................................................................
Csr Accesses214................................................................................................................................................................
External Register Set214................................................................................................................................................................
Chip Configuration214................................................................................................................................................................
Csr Architecture215................................................................................................................................................................
Register Summary215................................................................................................................................................................
Detailed Register Bit Descriptions218................................................................................................................................................................
Software Considerations254................................................................................................................................................................
Writing To The Control Registers254................................................................................................................................................................
Ecc Codes266................................................................................................................................................................
General Information269................................................................................................................................................................
Product Overview - Features269................................................................................................................................................................
Dma Controller271................................................................................................................................................................
Interrupter And Interrupt Handler271................................................................................................................................................................
Figure 4-1. Architectural Diagram For The Universe Ii271................................................................................................................................................................
Registers - Universe Ii Control And Status Registers (ucsr)276................................................................................................................................................................
Universe Ii Register Map277................................................................................................................................................................
Pci Arbitration282................................................................................................................................................................
Programming Details282................................................................................................................................................................
Interrupt Handling283................................................................................................................................................................
Hawk Mpic284................................................................................................................................................................
Sources Of Reset288................................................................................................................................................................
Soft Reset289................................................................................................................................................................
Universe Ii Chip Problems After A Pci Reset289................................................................................................................................................................
Error Notification And Handling290................................................................................................................................................................
Endian Issues291................................................................................................................................................................
Figure 5-3. Big-endian Mode292................................................................................................................................................................
Figure 5-4. Little-endian Mode293................................................................................................................................................................
Pci Domain294................................................................................................................................................................
Processor/memory Domain294................................................................................................................................................................
Mpic's Involvement294................................................................................................................................................................
Vmebus Domain295................................................................................................................................................................
Universe Ii's Involvement295................................................................................................................................................................
Rom/flash Initialization296................................................................................................................................................................
Motorola Computer Group Documents311................................................................................................................................................................
Related Specifications314................................................................................................................................................................

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