8259 Compatibility; Phb Detected Errors - Motorola MVME2400 Series Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
registers. If subsequent IPI's are initiated before the first is acknowledged,
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only one IPI will be generated. The IPI channels deliver interrupts in the
Direct Mode and can be directed to more than one processor.

8259 Compatibility

The MPIC provides a mechanism to support PC-AT compatible chip sets
using the 8259 interrupt controller architecture. After power on reset, the
MPIC defaults to 8259 pass-through mode. In this mode, if the OPIC is
enabled interrupts from external source number 0 (the interrupt signal from
the 8259 is connected to this external interrupt source on the MPIC) are
passed directly to processor 0. If the pass-through mode is disabled and the
OPIC is enabled, the 8259 interrupts are delivered using the priority and
distribution mechanisms of the MPIC.
MPIC does not interact with the vector fetch from the 8259 interrupt
controller.

PHB Detected Errors

PHB detected errors are grouped together and sent to the interrupt logic as
a singular interrupt source. The interrupt delivery mode for this interrupt is
distributed. When the OPIC is disabled, the PHB interrupt will be directly
passed on to processor 0 INT pin.
For system implementations where the MPIC controller is not used, the
PHB Detected Error condition will be made available by a signal which is
external to the Hawk ASIC. Presumably this signal would be connected to
an externally sourced interrupt input of a MPIC controller in a different
device. Since the MPIC specification defines external I/O interrupts to
operate in the distributed mode, the delivery mode of this error interrupt
should be consistent.
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