Sdram Size; I2C Eeproms; Sdram Base Address And Enable - Motorola MVME2400 Series Programmer's Reference Manual

System Memory Controller (SMC)

SDRAM Size

The SDRAM size control bits come up from power-up reset cleared to
zero. Once software has determined the correct size for an SDRAM block,
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it should set the block's size bits to match. The value programmed into the
size bits tells the Hawk how big the block is (for map decoding) and how
to translate that block's 60x addresses to SDRAM addresses.
Programming a block's size to non-zero also allows it to participate in
scrubbing if scrubbing is enabled.
After software programs the size bits, it should wait for a refresh to happen
before beginning to access SDRAM.

I2C EEPROMs

Most of the information needed to program the SDRAM speed attributes
and size is provided by EEPROM devices that are connected to Hawk's
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Serial Presence Detect (SPD).
Board designers can implement one EEPROM for each of Hawk's
SDRAM blocks or they can implement one EEPROM for several such
blocks. When using DIMMs, the board designer can use the EEPROM that
is provided on the DIMM.
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different device locations. Board designers should establish an I
EEPROM addressing scheme that will allow software to know which I
address to use to find information for each SDRAM block. For example,
hardware could always place the I
first address, block B at the second, etc. Whatever addressing scheme is
used should also deal with cases where multiple blocks are described by
one I

SDRAM Base Address and Enable

Each block needs to be programmed for a unique base address that is an
even multiple of its size. Once a block's speed attributes, size, and base
address have been programmed and time for at least one refresh has
passed, it can be enabled.
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C bus. The EEPROM devices contain data in a specific format called
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C EEPROMs that are used for SPD can be wired to appear at one of 8
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C EEPROM.
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C EEPROM for SDRAM block A at the
Computer Group Literature Center Web Site
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C
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C