Motorola MVME2400 Series Programmer's Reference Manual page 17

List of Tables
Table 1-1. MVME240x Features................................................................................1-2
Table 1-2. Default Processor Memory Map...............................................................1-6
Table 1-3. CHRP Memory Map Example..................................................................1-7
Table 1-4. PHB Register Values for CHRP Memory Map ........................................1-9
Table 1-5. PREP Memory Map Example.................................................................1-10
Table 1-6. PHB Register Values for PREP Memory Map .......................................1-11
Table 1-7. PCI CHRP Memory Map........................................................................1-12
Table 1-8. PHB PCI Register Values for CHRP Memory Map ...............................1-13
Table 1-9. Universe II PCI Register Values for CHRP Memory Map.....................1-14
Table 1-10. PCI PREP Memory Map.......................................................................1-15
Table 1-11. PHB PCI Register Values for PREP Memory Map ..............................1-16
Table 1-12. Universe II PCI Register Values for PREP Memory Map ....................1-17
Table 1-13. Universe II PCI Register Values for VMEbus Slave Map Example.....1-22
Table 1-14. VMEbus Slave Map Example...............................................................1-23
Table 1-15. 16550 Access Registers ........................................................................1-25
Table 1-16. MK48T59/559 Access Registers ..........................................................1-27
Table 1-17. VME Registers......................................................................................1-28
Table 1-18. Emulated Z8536 Access Registers........................................................1-33
Table 1-19. Z8536 CIO Port Pins Assignment.........................................................1-33
Table 2-1. PPC Slave Response Command Types .....................................................2-8
Table 2-2. PPC Master Transaction Profiles and Starting Offsets ...........................2-11
Table 2-3. PPC Master Write Posting Options.........................................................2-12
Table 2-4. PPC Master Read Ahead Options...........................................................2-13
Table 2-5. PPC Master Transfer Types ....................................................................2-14
Table 2-6. PPC Arbiter Pin Assignments.................................................................2-15
Table 2-7. PCI Slave Response Command Types....................................................2-23
Table 2-8. PCI Master Command Codes .................................................................2-27
Table 2-9. PCI Arbiter Pin Description....................................................................2-34
Table 2-10. Fixed Mode Priority Level Setting .......................................................2-35
Table 2-11. Mixed Mode Priority Level Setting ......................................................2-36
Table 2-12. Arbitration Setting ................................................................................2-37
Table 2-13. Address Modification for Little Endian Transfers................................2-40
Table 2-14. WDTxCNTL Programming ..................................................................2-44
Table 2-15. PHB Hardware Configuration ..............................................................2-49
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