Table 2-20. Cascade Mode Encoding; Table 2-21. Tie Mode Encoding - Motorola MVME2400 Series Programmer's Reference Manual

R (Reset Controller) Writing a one to this bit forces the controller
logic to be reset. This bit is cleared automatically when the reset
sequence is complete. While this bit is set, the values of all other
register are undefined.
EINTT (External Interrupt Type) This read only bit indicates the
external interrupt type: serial or parallel mode. When this bit is set,
MPIC is in serial mode for external interrupts 0 through 15. When this
bit is cleared, MPIC is in parallel mode for external interrupts.
M (Cascade Mode) If the Cascade mode (M) bit is cleared, the MPIC
is completely disabled. To activate the MPIC, set the M bit (mixed
mode), independent of the 8259's presence. The Cascade mode allows
cascading of an external 8259 pair connected to the first interrupt
source input pin (0). In the Pass Through mode, interrupt source 0 is
passed directly through to the processor 0 INT pin. MPIC is bypassed
in this scenario. In the mixed mode, the 8259 interrupts are delivered
using the priority and distribution mechanism of the MPIC. The
Vector/Priority and Destination registers for interrupt source 0 are used
to control the delivery mode for all 8259 generated interrupt sources.

Table 2-20. Cascade Mode Encoding

TIE (Tie Mode) Writing a one to this register bit will cause a tie in
external interrupt processing to swap back and forth between
processor 0 and 1. The first tie in external interrupt processing always
goes to Processor 0 after a reset. When this register bit is set to 0, a tie
in external interrupt processing will always go to Processor 0 (Mode
used on Version $02 of MPIC).
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M Mode
0 Pass Through
1 Mixed

Table 2-21. Tie Mode Encoding

T Mode
0 Processor 0 always selected
1 Swap between Processor's
Registers
2
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