Program And Data Memory; Schematic Diagram Of The External Memory Interface - Motorola 56F827 Hardware User Manual

2.2 Program and Data Memory

The 56F827EVM uses one bank of 128K×16-bit Fast Static RAM (GSI GS72116, labelled
U2) for external memory expansion; see the FSRAM schematic diagram in
This physical memory bank is split into two logical memory banks of 64Kx16-bits: one
for program memory and the other for data memory. By using the hybrid controller's
program strobe, PS, signal line along with the memory chip's A0 signal line, half of the
memory chip is selected when program memory accesses are requested and the other half
of the memory chip is selected when data memory access are requested. This memory
bank will operate with zero wait-state accesses while the 56F827 is running at 70MHz.
However, when running at 80MHz, the memory bank operates with four wait-state
accesses. This memory bank can be disabled by removing the jumper at JG3.
Figure 2-1. Schematic Diagram of the External Memory Interface
MOTOROLA
Freescale Semiconductor, Inc.
56F827
A0-A15
PS
D0-D15
RD
WR
JG3
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
Technical Summary
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Program and Data Memory
GS72116
A1-A16
A0
DQ0-DQ15
OE
WE
+3.3V
CE
Figure 2-1.
2-3