Single-Beat Reads/Writes; Address Pipelining; Page Holding; Sdram Speeds - Motorola MVME2400 Series Programmer's Reference Manual

and when the access time is reached, the SDRAM provides all four beats
of data, one on each clock. Hence, the SMC can provide the four beats of
data with zero idle clocks between each beat.

Single-beat Reads/Writes

Because of start-up, addressing, and completion overhead, single-beat
accesses to and from the PPC60x bus do not achieve data rates as high as
do four-beat accesses. Single-beat writes are the slowest because they
require that the SMC perform a read cycle then a write cycle to the
SDRAM in order to complete. Fortunately, in most PPC 60x systems,
single-beat accesses can be held to a minimum, especially with data cache
and copyback modes in place.

Address Pipelining

The SMC takes advantage of the fact that PPC60x processors can do
address pipelining. Many times while a data cycle is finishing, the PPC60x
processor begins a new address cycle. The SMC can begin the next
SDRAM access earlier when this happens, thus increasing throughput.

Page Holding

Further savings comes when the new address is close enough to a previous
one that it falls within an open page in the SDRAM array. When this
happens, the SMC can transfer the data for the next cycle without having
to wait to activate a new page in SDRAM. In the SMC this feature is
referred to as page holding.

SDRAM Speeds

The SDRAM that the Hawk ASIC controls uses the 60x clock. The SMC
can be configured to operate at several different 60x clock frequencies
using SDRAMs that have various speed characteristics. The bits that
control this configuration are located in the SDRAM Speed Attributes
Register, which is described in the Register portion of this section. Refer
to the table below for some specific timing numbers.
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Functional Description
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