Motorola MVME2400 Series Programmer's Reference Manual page 10

Nesting of Interrupt Events...............................................................................2-53
Spurious Vector Generation ..............................................................................2-53
Interprocessor Interrupts (IPI) ..........................................................................2-53
8259 Compatibility ...........................................................................................2-54
PHB Detected Errors ........................................................................................2-54
Timers ...............................................................................................................2-55
Interrupt Delivery Modes..................................................................................2-55
Block Diagram Description ..............................................................................2-56
Program Visible Registers .........................................................................2-58
Interrupt Pending Register (IPR) ...............................................................2-58
Interrupt Selector (IS) ................................................................................2-58
Interrupt Request Register (IRR)...............................................................2-59
In-Service Register (ISR) ..........................................................................2-59
Interrupt Router .........................................................................................2-59
Programming Notes ..........................................................................................2-61
External Interrupt Service..........................................................................2-61
Reset State .................................................................................................2-62
Operation ..........................................................................................................2-63
Interprocessor Interrupts............................................................................2-63
Dynamically Changing I/O Interrupt Configuration .................................2-63
EOI Register ..............................................................................................2-63
Interrupt Acknowledge Register................................................................2-64
8259 Mode.................................................................................................2-64
Current Task Priority Level.......................................................................2-64
Architectural Notes ...........................................................................................2-64
Effects of Interrupt Serialization.......................................................................2-65
Registers...................................................................................................................2-65
PPC Registers ...................................................................................................2-66
Vendor ID/Device ID Registers ................................................................2-67
Revision ID Register .................................................................................2-68
General Control-Status/Feature Registers .................................................2-69
PPC Arbiter/PCI Arbiter Control Registers...............................................2-71
Hardware Control-Status/Prescaler Adjust Register .................................2-74
PPC Error Test/Error Enable Register.......................................................2-77
PPC Error Status Register..........................................................................2-79
PPC Error Address Register ......................................................................2-81
PPC Error Attribute Register .....................................................................2-82
PCI Interrupt Acknowledge Register ........................................................2-83
PPC Slave Address (0,1 and 2) Registers..................................................2-84
PPC Slave Offset/Attribute (0, 1 and 2) Registers ....................................2-85
PPC Slave Address (3) Register ................................................................2-86
PPC Slave Offset/Attribute (3) Registers ..................................................2-87
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