Sdram Organization - Motorola MVME2400 Series Programmer's Reference Manual

Table 3-1. 60x Bus to SDRAM Estimated Access Timing at 100MHz with
PC100 SDRAMs (CAS_latency of 2) (Continued)
Access Type
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Hit
1-Beat Write after idle,
SDRAM Bank Active or Inactive
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Miss
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Hit
Notes SDRAM speed attributes are programmed for the following:
CAS_latency = 2, tRCD = 2 CLK Periods, tRP = 2CLK Periods,
tRAS = 5 CLK Periods, tRC = 7 CLK Periods, tDP = 2 CLK
Periods, and the swr dpl bit is set in the SDRAM Speed
Attributes Register.
The Hawk is configured for "no external registers" on the
SDRAM control signals.

SDRAM Organization

The SDRAM is organized as 1, 2, 3, 4, 5, 6, 7, or 8 blocks, 72 bits wide
with 64 of the bits being normal data and the other 8 being checkbits. The
72 bits of SDRAM for each block can be made up of x4, x8, or x16
components or of 72-bit DIMMs that are made up of x4 or x8 components.
The 72-bit, unbuffered DIMMs can be used as long as AC timing is met
and they use the components listed. All components must be organized
with 4 internal banks.
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Access Time Comments
(tB1-tB2-tB3-tB4)
5
5
13
8
Functional Description
3-9
3