Functional Description; Performance; Four-Beat Reads/Writes; Figure 3-4. Hawk's System Memory Controller Block Diagram - Motorola MVME2400 Series Programmer's Reference Manual

System Memory Controller (SMC)
PPC60x Ctrl
3
PPC60x Attr
ADDRESS
DECODER
PPC60x Addr
I2C Bus
INTERFACE
PPC60x Data

Figure 3-4. Hawk's System Memory Controller Block Diagram

Functional Description

The following sections describe the logical function of the SMC. The SMC
has interfaces between the PowerPC bus and SDRAM, ROM/Flash, and its
Control and Status Register sets (CSR).

Performance

Four-beat Reads/Writes

The SMC performs best when doing bursting (4-beat accesses). This is
made possible by the burst nature of synchronous DRAMs. When the
PPC60x master begins a burst read to SDRAM, the SMC starts the access
3-6
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PPC60x
SLAVE
INTERFACE
REFRESHER
PPC60x
ARBITER
STATUS
/CONTROL
I2C
REGISTERS
DATA
MULTIPLEXOR
SDRAM
&
ROM/Flash
CONTROL
SDRAM
/SCRUBBER
ADDRESS
MULTIPLEXOR
SDRAM
ERROR
JTAG
LOGGER
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MEM Ctrl
MEM Addr
MEM Data