Motorola MVME2400 Series Programmer's Reference Manual page 320

Hawk with SDRAMs
board configuration information
bridge
PHB viii, 2-1
PowerPC to PCI Local Bus Bridge viii,
2-1
bus cycle types
on the PCI bus
Bus Hog
PPC master device
bus interface (60x)
to SMC 3-12
byte ordering x
byte, definition x
C
cache coherency
SMC 3-14
cache coherency restrictions
cache support 2-26,
CHRP memory map
PHB PCI Register Values
register values
Universe II PCI Register Values
CHRP memory map example
CLK FREQUENCY
CLK Frequency Register
SMC 3-44
clock frequency 3-44
combining, merging, and collapsing
command types 2-23
from PCI Master
PPC slave 2-8
CONFIG_ADDRESS Register
CONFIG_DATA Register
I
configuration options
N
Hawk 3-34
configuration registers
D
configuration requirements
E
Hawk 3-34
X
configuration type
as used by PHB
IN-2
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3-2
1-23
2-30
2-14
3-14
2-30
1-13
1-9
1-14
1-7
3-44
2-28
2-27
2-100
2-103
2-19
2-32
contention
between PCI and PPC 2-44
contention handling
explained (PHB) 2-45
control bit descriptions 3-38
control bit, definition x
conventions, manual ix
Critical Word First (CWF)
as supported by PCI Master
CSR accesses
SMC 3-34
CSR architecture
SMC 3-35
CSR base address 3-35
CSR reads and writes 3-35
CWF burst transfers
explained 2-27
cycle types
SMC 3-15
D
data
discarded from prefetched reads
data parity
PPC 2-17
Data Parity Error Address Register
SMC 3-60
Data Parity Error Log Register
SMC 3-59
Data Parity Error Lower Data Register
SMC 3-61
Data Parity Error Upper Data Register
SMC 3-60
data throughput
PPC Slave to PCI Master
data transfer
PPC Master rates 2-10
relationship between PCI Slave and
PPC60x bus 2-11
data transfers
SMC 3-13
decimal number ix
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Index
2-27
2-13
2-9