Cache Coherency; Cache Coherency Restrictions; L2 Cache Support - Motorola MVME2400 Series Programmer's Reference Manual

System Memory Controller (SMC)
During any address transfer cycle on the PPC60x, the SMC checks each of
the 4 8-bit PPC60x address lanes and its corresponding AP signal for odd
parity. If any of the 4 lanes has even parity, the SMC logs the error in the
CSR and can generate a machine check if so enabled.
3
Note
Refer to the
document for additional control register details.

Cache Coherency

The SMC supports cache coherency to SDRAM only. It does this by
monitoring the ARTRY_ control signal on the PPC60x bus and behaving
appropriately when it is asserted. When ARTRY_ is asserted, if the access
is a SDRAM read, the SMC does not source the data for that access. If the
access is a SDRAM write, the SMC does not write the data for that access.
Depending upon when the retry occurs, the SMC may cycle the SDRAM
even though the data transfer does not happen.

Cache Coherency Restrictions

The PPC60x GBL_ signal must not be asserted in the CSR areas.

L2 Cache Support

The SMC provides support for a look-aside L2 cache (only at 66.67MHz)
by implementing a hold-off input, L2CLM_. On cycles that select the
SMC, the SMC samples L2CLM_ on the second rising edge of the CLK
input after the assertion of TS_. If L2CLM_ is high, the SMC responds
normally to the cycle. If it is low, the SMC ignores the cycle.
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The SMC does not generate address parity because it is not a
PPC60x address master.
Address Parity Error Log Register
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