Table 3-16. Trc Encoding; Table 3-17. Tras Encoding - Motorola MVME2400 Series Programmer's Reference Manual

Note Writing so as to change cl3 from 1 to 0 or vice-versa causes the
SMC to perform a mode-register-set operation to the SDRAM
array. The mode-register-set operation updates the SDRAM's
CAS_latency to match cl3.
trc0,1,2 Together trc0,1,2 determine the minimum number of clock
cycles that the SMC assumes the SDRAM requires to satisfy its Trc
parameter. These bits are encoded as follows:
trc0,1,2
%000
%001
%010
%011
%100
%101
%110
%111
tras0,1 Together tras0,1 determine the minimum number of clock
cycles that the SMC assumes the SDRAM requires to satisfy its tRAS
parameter. These bits are encoded as follows:
tras0,1
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Table 3-16. Trc Encoding

Minimum Clocks for Trc
reserved
reserved

Table 3-17. tras Encoding

Minimum Clocks for tras
%00
%01
%10
%11
Programming Model
8
9
10
11
6
7
4
5
6
7
3
3-69