Ecc; Cycle Types; Error Reporting - Motorola MVME2400 Series Programmer's Reference Manual

ECC (Error Correction Code)
The SMC performs single-bit error correction and double-bit error
detection for SDRAM across 64 bits of data using 8 check bits. No
checking is provided for ROM/Flash.

Cycle Types

To support ECC, the SMC always deals with SDRAM using full width
(72-bit) accesses. When the PPC60x bus master requests any size read of
SDRAM, the SMC reads the full width at least once. When the PPC60x
bus master requests a four-beat write to SDRAM, the SMC writes all 72
bits four times. When the PPC60x bus master requests a single-beat write
to SDRAM, the SMC performs a full width read cycle to SDRAM, merges
in the appropriate PPC60x bus write data, and writes full width back to
SDRAM.

Error Reporting

The SMC checks data from the SDRAM during single- and four-beat
reads, during single-beat writes, and during scrubs.
actions it takes for different errors during these accesses.
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Functional Description
Table 3-6 shows the
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