Table 3-1. 60X Bus To Sdram Estimated Access Timing At 100Mhz With Pc100 Sdrams (Cas_Latency Of 2) - Motorola MVME2400 Series Programmer's Reference Manual

System Memory Controller (SMC)
Table 3-1. 60x Bus to SDRAM Estimated Access Timing at 100MHz with
3
Access Type
4-Beat Read after idle,
SDRAM Bank Inactive
4-Beat Read after idle,
SDRAM Bank Active - Page Miss
4-Beat Read after idle,
SDRAM Bank Active - Page Hit
4-Beat Read after 4-Beat Read,
SDRAM Bank Active - Page Miss
4-Beat Read after 4-Beat Read,
SDRAM Bank Active - Page Hit
4-Beat Write after idle,
SDRAM Bank Active or Inactive
4-Beat Write after 4-Beat Write,
SDRAM Bank Active - Page Miss
4-Beat Write after 4-Beat Write,
SDRAM Bank Active - Page Hit
1-Beat Read after idle,
SDRAM Bank Inactive
1-Beat Read after idle,
SDRAM Bank Active - Page Miss
1-Beat Read after idle,
SDRAM Bank Active - Page Hit
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Miss
3-8
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PC100 SDRAMs (CAS_latency of 2)
Access Time
(tB1-tB2-tB3-tB4)
10-1-1-1
12-1-1-1
7-1-1-1
5-1-1-1
2.5-1-1-1
4-1-1-1
6-1-1-1
3-1-1-1
10
12
7
8
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Comments
2.5-1-1-1 is an average of 2-
1-1-1 half of the time and 3-
1-1-1 the other half.
3-1-1-1 for the second burst
write after idle.
2-1-1-1 for subsequent burst
writes.