Pci Interrupt Acknowledge Register - Motorola MVME2400 Series Programmer's Reference Manual

Address $FEFF002C
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation R
Reset $00
WP (Write Post Completion) This bit is set when the PCI master
detects an error while completing a write post transfer.
XIDx (PPC Master ID) This field contains the ID of the PPC master
which originated the transfer in which the error occurred. The
encoding scheme is identical to that used in the GCSR register
COMMx (PCI Command) This field contains the PCI command of
the PCI transfer in which the error occurred.
BYTEx (PCI Byte Enable) This field contains the PCI byte enables of
the PCI transfer in which the error occurred. A set bit designates a
selected byte.

PCI Interrupt Acknowledge Register

The PCI Interrupt Acknowledge Register (PIACK) is a read only register
that is used to initiate a single PCI Interrupt Acknowledge cycle. Any
single byte or combination of bytes may be read from, and the actual byte
enable pattern used during the read will be passed on to the PCI bus. Upon
completion of the PCI interrupt acknowledge cycle, the PHB will present
the resulting vector information obtained from the PCI bus as read data.
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1 1 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8
EATTR
R
$00
Registers
1 2 2 2 2 2 2 2 2 2 2
9 0 1 2 3 4 5 6 7 8 9
2
3 3
0 1
2-83