Lm/Sig Status Register - Motorola MVME2400 Series Programmer's Reference Manual

SET_LM1 Writing a 1 to this bit will set the LM1 status bit.
SET_LM0 Writing a 1 to this bit will set the LM0 status bit.
CLR_SIG1 Writing a 1 to this bit will clear the SIG1 status bit.
CLR_SIG0 Writing a 1 to this bit will clear the SIG0 status bit.
CLR_LM1 Writing a 1 to this bit will clear the LM1 status bit.
CLR_LM0 Writing a 1 to this bit will clear the LM0 status bit.

LM/SIG Status Register

The LM/SIG Status Register is an 8-bit register located at ISA I/O address
x1001. This register, in conjunction with the LM/SIG Control Register,
provides a method to generate interrupts. The Universe II ASIC is
programmed so that this register can be accessed from the VMEbus to
provide a capability to generate software interrupts to the onboard
processor(s) from the VMEbus.
REG
BIT SD7 SD6
FIELD EN EN
SIG1 SIG0
OPER
RESET 0 0
EN_SIG1 When the EN_SIG1 bit is set, a LM/SIG Interrupt 1 is
generated if the SIG1 bit is asserted.
EN_SIG0 When the EN_SIG0 bit is set, a LM/SIG Interrupt 0 is
generated if the SIG0 bit is asserted.
EN_LM1 When the EN_LM1 bit is set, a LM/SIG Interrupt 1 is
generated and the LM1 bit is asserted.
EN_LM0 When the EN_LM0 bit is set, a LM/SIG Interrupt 0 is
generated and the LM0 bit is asserted.
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LM/SIG Status Register - Offset $1001
SD5 SD4 SD3
EN EN SIG1
LM1 LM0
R/W
0 0
ISA Local Resource Bus
SD2 SD1
SIG0 LM1
READ-ONLY
0 0 0
1
SD0
LM0
0
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