Motorola MVME2400 Series Programmer's Reference Manual page 9

ISA DMA Channels ......................................................................................... 1-34
CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Introduction ............................................................................................................... 2-1
Overview ............................................................................................................ 2-1
Features .............................................................................................................. 2-1
Block Diagram........................................................................................................... 2-3
Functional Description .............................................................................................. 2-4
Architectural Overview ...................................................................................... 2-4
PPC Bus Interface .............................................................................................. 2-5
PPC Address Mapping ................................................................................ 2-5
PPC Slave.................................................................................................... 2-7
PPC FIFO .................................................................................................... 2-9
PPC Master................................................................................................ 2-10
PPC Arbiter ............................................................................................... 2-15
PPC Parity ................................................................................................. 2-17
PPC Bus Timer.......................................................................................... 2-17
PCI Bus Interface ............................................................................................. 2-19
PCI Address Mapping ............................................................................... 2-19
PCI Slave................................................................................................... 2-22
PCI FIFO ................................................................................................... 2-26
PCI Master ................................................................................................ 2-26
Generating PCI Cycles .............................................................................. 2-30
PCI Arbiter ................................................................................................ 2-34
Endian Conversion ........................................................................................... 2-38
When PPC Devices are Big-Endian .......................................................... 2-38
When PPC Devices are Little Endian ....................................................... 2-39
PHB Registers ........................................................................................... 2-40
Error Handling.................................................................................................. 2-41
Watchdog Timers.............................................................................................. 2-42
PCI/PPC Contention Handling ......................................................................... 2-44
Transaction Ordering........................................................................................ 2-47
PHB Hardware Configuration .......................................................................... 2-49
Multi-Processor Interrupt Controller (MPIC) Functional Description.................... 2-50
MPIC Features:................................................................................................. 2-50
Architecture ...................................................................................................... 2-51
External Interrupt Interface .............................................................................. 2-51
CSR's Readability ............................................................................................ 2-52
Interrupt Source Priority................................................................................... 2-52
Processor's Current Task Priority..................................................................... 2-53
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