Rom A Base/Size Register - Motorola MVME2400 Series Programmer's Reference Manual

ROM A Base/Size Register

Address
$FEF80050
Bit
Name
ROM A BASE
Operation
READ/WRITE
Reset
$FF0 PL
Writes to this register must be enveloped by a period of time in which no
accesses to ROM/Flash Block A, occur. A simple way to provide the
envelope is to perform at least two accesses to this or another of the SMC's
registers before and after the write.
ROM A BASE These control bits define the base address for
ROM/Flash Block A. ROM A BASE bits 0-11 correspond to PPC60x
address bits 0 - 11 respectively. For larger ROM/Flash sizes, the lower
significant bits of ROM A BASE are ignored. This means that the
block's base address will always appear at an even multiple of its size.
ROM A BASE is initialized to $FF0 at power-up or local bus reset.
Note
rom_a_64 rom_a_64 indicates the width of ROM/Flash being used
for Block A. When rom_a_64 is cleared, Block A is 16 bits wide,
where each half of SMC interfaces to 8 bits. When rom_a_64 is set,
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Note that in addition to the programmed address, the first 1
Mbyte of Block A also appears at $FFF00000 - $FFFFFFFF if
the rom_a_rv bit is set and the rom_b_rv bit is cleared.
Also note that the combination of ROM_A_BASE and
rom_a_siz should never be programmed such that ROM/Flash
Block A responds at the same address as the CSR, SDRAM,
External Register Set, or any other slave on the PowerPC bus.
Programming Model
READ ZERO
X
3
3-53