Pci Command/Status Registers - Motorola MVME2400 Series Programmer's Reference Manual

PCI Command/Status Registers

The Command Register (COMMAND) provides course control over the
PHB ability to generate and respond to PCI cycles. The bits within the
COMMAND register are defined as follows:
Offset $04
Bit
Name STATUS
Operation
Reset
IOSP (IO Space Enable) If set, the PHB will respond to PCI I/O
accesses when appropriate. If cleared, the PHB will not respond to PCI
I/O space accesses.
MEMSP (Memory Space Enable) If set, the PHB will respond to PCI
memory space accesses when appropriate. If cleared, the PHB will not
respond to PCI memory space accesses.
MSTR (Bus Master Enable) If set, the PHB may act as a master on
PCI. If cleared, the PHB may not act as a PCI master.
PERR (Parity Error Response) If set, the PHB will check parity on all
PCI transfers. If cleared, the PHB will ignore any parity errors that it
detects and continue normal operation.
SERR (System Error Enable) This bit enables the SERR_ output pin.
If clear, the PHB will never drive SERR_. If set, the PHB will drive
SERR_ active when a system error is detected.
The Status Register (STATUS) is used to record information for PCI bus
related events. The bits within the STATUS register are defined as follows:
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COMMAND
Registers
2
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