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Motorola MVME2300SC Series Installation And Use Manual

Vme processor module, v2300sca/ih2
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MVME2300SC
VME Processor Module
Installation and Use
V2300SCA/IH2
Edition of March 2001

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  Summary of Contents for Motorola MVME2300SC Series

  • Page 1 MVME2300SC VME Processor Module Installation and Use V2300SCA/IH2 Edition of March 2001...
  • Page 2 All rights reserved. Printed in the United States of America. ® Motorola and the Motorola logo are registered trademarks of Motorola, Inc. ® PowerPC is a registered trademark of International Business Machines Corporation and is used by Motorola with permission.
  • Page 3 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
  • Page 4 Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
  • Page 5 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
  • Page 6 If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
  • Page 7: Table Of Contents

    Contents About this Manual Summary of Changes ....................xvi Overview of Contents ....................xvi Comments and Suggestions ..................xvii Conventions Used in This Manual................xviii CHAPTER 1 Hardware Preparation and Installation Getting Started ......................1-1 Overview of Installation Procedure ..............1-1 Equipment Required ...................1-3 Guidelines for Unpacking ...................1-4 ESD Precautions ....................1-4 Preparing the Board ....................1-5 MVME2300SC ....................1-6...
  • Page 8 Autoboot ......................2-7 ROMboot......................2-8 Network Boot ..................... 2-9 Restarting the System ....................2-9 Reset ......................... 2-10 Abort......................... 2-11 Break ........................ 2-11 Diagnostic Facilities ....................2-11 CHAPTER 3 PPCBug Firmware Overview ........................3-1 PPCBug Basics ......................3-1 PPCBug Implementation ................... 3-2 Memory Requirements ..................
  • Page 9 PCI Mezzanine Card Connectors - J21 through J24.........5-15 APPENDIX A Specifications Board Specifications ....................A-1 Cooling Requirements ....................A-3 EMC Regulatory Compliance...................A-4 APPENDIX B Troubleshooting Solving Startup Problems ..................B-1 APPENDIX C Related Documentation Motorola Computer Group Documents ..............C-1 Manufacturers’ Documents..................C-2 Related Specifications....................C-5...
  • Page 10 Glossary Index...
  • Page 11 List of Figures Figure 1-1. MVME2300SC Layout ................1-7 Figure 1-2. General-Purpose Software-Readable Header........1-10 Figure 1-3. Typical Single-width PMC Module Placement on MVME2300SC ..1-12 Figure 1-4. PMCspan-002 Installation on an MVME2300SC.........1-15 Figure 1-5. PMCspan-010 Installation on a PMCspan-002/MVME2300SC ..1-17 Figure 2-1. MVME2300SC/Firmware System Startup ..........2-3 Figure 4-1.
  • Page 13 List of Tables Table 1-1. Startup Overview ..................1-1 Table 1-2. MVME2300SC Jumper Settings ..............1-6 Table 2-1. MVME2300SC Front Panel Controls............2-1 Table 3-1. Debugger Commands ................3-4 Table 3-2. Diagnostic Test Groups................3-8 Table 4-1. MVME2300SC Features................4-1 Table 4-2. Power Requirements .................4-4 Table 4-3. PPC604-Bus-to-DRAM Timing — 60ns Page Devices ......4-7 Table 4-4.
  • Page 15: About This Manual

    About This Manual MVME2300SC VME Processor Module Installation and Use provides information you will need to install and use your MVME2300SC VME processor module. It includes instructions for hardware preparation and installation; a board-level hardware overview; and firmware-related general information and startup instructions. The MVME2300SC VME processor module is based on an MPC604 PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/or P2 I/O.
  • Page 16: Summary Of Changes

    Summary of Changes This is the third edition of MVME2300SC Installation and Use. It supersedes the April 1999 edition and incorporates the following updates. Date Description of Change April 1999 Tables C-8 and C-10 were updated to supply corrected pinout information for PMC connectors J14 and J24.
  • Page 17: Comments And Suggestions

    Documentation, lists all documentation related to the MVME2300SC. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:...
  • Page 18: Conventions Used In This Manual

    Conventions Used in This Manual The following typographical conventions are used in this document: bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files.
  • Page 19: Getting Started

    1Hardware Preparation and Installation Getting Started This chapter provides unpacking instructions, hardware preparation guidelines, and installation instructions for the MVME2300SC VME processor module. The section below supplies an overview of the preparation and startup process. Overview of Installation Procedure The following table lists the things you will need to do to use this board and tells where to find the information you need to perform each step.
  • Page 20 Hardware Preparation and Installation Table 1-1. Startup Overview (Continued) What you need to do ... Refer to ... page ... Install the primary Installing the Hardware, Primary PMCspan Module 1-13 PMCspan module (if For additional information on PMCspan modules, refer used).
  • Page 21: Equipment Required

    Getting Started Table 1-1. Startup Overview (Continued) What you need to do ... Refer to ... page ... Examine and/or change 3-11 ENV - Set Environment environmental You may also wish to obtain the PPCBug Firmware parameters. Package User’s Manual, listed in Appendix C, Related Documentation.
  • Page 22: Guidelines For Unpacking

    This section applies to all hardware installations you may perform that involve the MVME2300SC board. Motorola strongly recommends the use of an antistatic wrist strap and a conductive foam pad when you install or upgrade the board. Electronic components can be extremely sensitive to ESD. After removing the board from the chassis or from its protective wrapper, place the board flat on a grounded, static-free surface, component side up.
  • Page 23: Preparing The Board

    Preparing the Board Turn the system’s power off before you perform these procedures. Failure to turn the power off before opening the enclosure can result in personal injury or damage to the equipment. Hazardous voltage, current, and energy Warning levels are present in the chassis. Hazardous voltages may be present on power switch terminals even when the power switch is off.
  • Page 24: Mvme2300Sc

    Hardware Preparation and Installation MVME2300SC Figure 1-1 illustrates the placement of the jumper headers, connectors, and various other components on the MVME2300SC. Manually configurable jumper headers on the MVME2300SC are listed in the following table (with default settings enclosed in brackets). Table 1-2.
  • Page 25: Figure 1-1. Mvme2300Sc Layout

    Preparing the Board SCON Figure 1-1. MVME2300SC Layout...
  • Page 26: Flash Bank Selection (J8)

    Hardware Preparation and Installation Flash Bank Selection (J8) The MVME2300SC VMEmodule has provision for 1MB of 8-bit Flash memory for the on-board firmware (or for customer-specific applications) in two 32-pin PLCC sockets that constitute Flash bank B. In addition, the MVME2300SC accommodates 4MB of firmware resident on four soldered-in devices (Flash bank A) specifically for customer use.
  • Page 27: Vmebus System Controller (J9)

    Preparing the Board VMEbus System Controller (J9) The MVME2300SC is factory-configured in ‘‘automatic’’ system controller mode (i.e., a jumper is installed across pins 2 and 3 of header J9). This means that at system power-up or reset, the MVME2300SC determines whether it is system controller by its position on the bus; if it occupies slot 1 on the VME system, it configures itself as the system controller.
  • Page 28: Pmcs

    Hardware Preparation and Installation PPCBug INSTALLED Bit 0 (SRH0) Reserved for future use Bit 1 (SRH1) Reserved for future use Bit 2 (SRH2) Reserved for future use Bit 3 (SRH3) Reserved for future use Bit 4 (SRH4) Reserved for future use Bit 5 (SRH5) Reserved for future use Bit 6 (SRH6)
  • Page 29: Installing The Hardware

    Installing the Hardware Installing the Hardware This section covers: Installation of PMCs and PMCspan modules on the MVME2300SC Installation of the assembly in a VME chassis System considerations relevant to the installation PMC Modules PCI mezzanine card (PMC) modules mount on top of the MVME2300SC, and/or on a PMCspan module.
  • Page 30: Figure 1-3. Typical Single-Width Pmc Module Placement On Mvme2300Sc

    Hardware Preparation and Installation 3. Remove the PCI filler plate from the selected PMC slot in the front panel of the MVME2300SC. If you are installing a double-width PMC, remove the filler plates from both PMC slots. 4. Slide the front panel(s) of the PMC module into the front panel opening(s) from behind and place the PMC module on top of the MVME2300SC.
  • Page 31: Primary Pmcspan Module

    Installing the Hardware Primary PMCspan Module To install a PMCspan-002 PCI expansion module on your MVME2300SC, refer to Figure 1-4 and perform the following steps. This procedure assumes that you have read the user’s manual that was furnished with the PMCspan module, and that you have installed the selected PMCs on the PMCspan according to the instructions given in the PMCspan and PMC manuals.
  • Page 32 Hardware Preparation and Installation 4. Place the PMCspan on top of the MVME2300SC module. Align the mounting holes in each corner to the standoffs, and align PMCspan connector P4 with MVME2300SC connector J6. 5. Gently press the PMCspan and MVME2300SC together, making sure that P4 is fully seated into J6.
  • Page 33: Figure 1-4. Pmcspan-002 Installation On An Mvme2300Sc

    Installing the Hardware SCREWS WITH SMALLER HEADS HERE 2388 9810 Figure 1-4. PMCspan-002 Installation on an MVME2300SC 1-15...
  • Page 34: Secondary Pmcspan Module

    Hardware Preparation and Installation Secondary PMCspan Module The PMCspan-010 PCI expansion module mounts on top of a PMCspan- 002 PCI expansion module. To install a PMCspan-010 on your MVME2300SC, refer to Figure 1-5 and perform the following steps. This procedure assumes that you have read the user’s manual that was furnished with the PMCspan, and that you have installed the selected PMCs on the PMCspan according to the instructions given in the PMCspan and PMC manuals.
  • Page 35: Figure 1-5. Pmcspan-010 Installation On A Pmcspan-002/Mvme2300Sc

    Installing the Hardware SCREWS WITH SMALLER HEADS HERE 2065 9708 Figure 1-5. PMCspan-010 Installation on a PMCspan-002/MVME2300SC 1-17...
  • Page 36: Mvme2300Sc

    Hardware Preparation and Installation 6. Gently press the two PMCspan modules together, making sure that P3 is fully seated in J3. 7. Insert the four short Phillips screws through the holes at the corners of PMCspan-010 and into the standoffs on the primary PMCspan- 002.
  • Page 37 5. Secure the MVME2300SC (and PMCspan modules if used) in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions. Some VME backplanes (e.g., those used in Motorola "Modular Note Chassis" systems) have an autojumpering feature for automatic propagation of the IACK and BG signals.
  • Page 38: System Console Terminal

    Hardware Preparation and Installation 7. If you intend to use PPCBug interactively, connect the terminal that is to be used as the PPCBug system console to the port on DEBUG the front panel of the MVME2300SC. In normal operation, the host CPU controls MVME2300SC operation via the VMEbus Universe registers.
  • Page 39: Installation Considerations

    Installing the Hardware Installation Considerations The MVME2300SC draws power from VMEbus backplane connectors P1 and P2. P2 is also used for the upper 16 bits of data in 32-bit transfers, and for the upper 8 address lines in extended addressing mode. The MVME2300SC may not function properly without its main board connected to VMEbus backplane connectors P1 and P2.
  • Page 40 Hardware Preparation and Installation one MVME2300SC processor to broadcast a signal to any other MVME2300 series processors. All eight registers are accessible from any local processor as well as from the VMEbus. 1-22 Computer Group Literature Center Web Site...
  • Page 41: Introduction

    2Startup and Operation Introduction This chapter provides information on powering up the MVME2300SC VME processor module after its installation in a system, and describes the functionality of the switches, status indicators, and I/O ports on the front panels of the MVME2300SC and PMCspan modules. For programming information, consult the MVME2300 Series VME Processor Module Programmer’s Reference Guide as listed in Appendix C, Related Documentation.
  • Page 42: Initial Conditions

    Startup and Operation Table 2-1. MVME2300SC Front Panel Controls Control/Indicator Function BRDFAIL∗ signal line is active. LED (yellow) Board failure. Lights when the DBB∗ (Data Bus Busy) signal line on LED (green) CPU activity. Lights when the the processor bus is active. MVME2300SC is functioning as LED (green) System controller.
  • Page 43: Applying Power

    Applying Power Applying Power When you power up (or when you reset) the system, the firmware executes some self-checks and proceeds to the hardware initialization. The system startup flows in a predetermined sequence, following the hierarchy inherent in the processor and the MVME2300SC hardware. The figure below charts the flow of the basic initialization sequence that takes place during system startup.
  • Page 44: Pre-Startup Checklist

    Startup and Operation Pre-Startup Checklist Before you power up the MVME2300SC system, be sure that the following conditions exist: 1. Jumpers and/or configuration switches on the MVME2300SC VME processor module and associated equipment are set as required for your particular application. 2.
  • Page 45: Bringing Up The Board

    Bringing up the Board Bringing up the Board The MVME2300SC comes with PPCBug firmware installed. For the firmware to operate properly with the board, you must follow the steps below. Inserting or removing boards with power applied may damage board components.
  • Page 46 Startup and Operation 5. Refer to the setup procedure for your particular chassis or system for details concerning the installation of the MVME2300SC and the implementation of the SCbus. 6. Confirm that the terminal to be used as the PPCBug system console is connected to the DB9 connector, J2, on the front panel of DEBUG...
  • Page 47: Autoboot

    Bringing up the Board 9. Before using the MVME2300SC after the initial installation, set the date and time using the following command line structure: SET [mmddyyhhmm]|[<+/-CAL>;C] PPC-Bug> For example, the following command line starts the real-time clock and sets the date and time to 10:37 a.m., November 7, 2001: SET 1107011037 PPC-Bug>...
  • Page 48: Romboot

    Startup and Operation Although you can use streaming tape to autoboot, the same power supply must be connected to the tape drive, the controller, and the MVME2300SC. At power-up, the tape controller will position the Caution streaming tape to the load point where the volume ID can correctly be read and used.
  • Page 49: Network Boot

    Restarting the System Network Boot Network Auto Boot is a software routine in the PPCBug firmware which provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device. The Network Auto Boot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing boot media is found or until the list is exhausted.
  • Page 50: Reset

    Startup and Operation same time. This feature can be helpful in the event that your setup/operation parameters are corrupted or do not meet a sanity check. Refer to the ENV command description in Chapter 3 for the ROM defaults. Reset Powering up the MVME2300SC initiates a system reset.
  • Page 51: Abort

    Diagnostic Facilities Abort Aborts are invoked by pressing and releasing the switch on the ABORT MVME2300SC front panel. When you invoke an abort while executing a user program (running target code), a snapshot of the processor state is stored in the target registers. This characteristic makes aborts most appropriate for terminating user programs that are being debugged.
  • Page 52 Startup and Operation If you are in the debugger directory, you can switch to the diagnostic directory with the debugger command Switch Directories (SD). The diagnostic prompt appears. Refer to the PPCBug Diagnostics PPC-Diag> Manual for complete descriptions of the diagnostic routines available and instructions on how to invoke them.
  • Page 53: Overview

    Related Documentation. PPCBug Basics The PowerPC debug firmware, PPCBug, is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation. PPCBug provides a high degree of functionality, user friendliness, portability, and ease of maintenance.
  • Page 54: Ppcbug Implementation

    PPCBug Firmware PPCBug consists of three parts: A command-driven, user-interactive software debugger, described in the PPCBug Firmware Package User’s Manual. It is hereafter referred to as “the debugger” or “PPCBug”. A command-driven diagnostics package for the MVME2300SC hardware, hereafter referred to as “the diagnostics.” The diagnostics package is described in the PPCBug Diagnostics Manual.
  • Page 55: Memory Requirements

    Using PPCBug Memory Requirements PPCBug requires a maximum of 512KB of read/write memory (i.e., DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F80000 to $03FFFFFF.
  • Page 56: Debugger Commands

    PPCBug Firmware A debugger command is made up of the following parts: The command name, either uppercase or lowercase (e.g., MD or md). Any required arguments, as specified by the command. At least one space before the first argument. Precede all other arguments with either a space or comma.
  • Page 57 Debugger Commands Table 3-1. Debugger Commands (Continued) Command Description Block of Memory Verify Concurrent Mode NOCM No Concurrent Mode CNFG Configure Board Information Block Checksum CSAR PCI Configuration Space READ Access CSAW PCI Configuration Space WRITE Access Data Conversion Block of Memory Move One Line Disassembler Dump S-Records ECHO...
  • Page 58 PPCBug Firmware Table 3-1. Debugger Commands (Continued) Command Description I/O Physical (Direct Disk Access) I/O Teach for Configuring Disk Controller Idle MPU Register Display Idle MPU Register Modify Idle MPU Register Set Load S-Records from Host Macro Define/Display NOMA Macro Delete Macro Edit Enable Macro Listing NOMAL...
  • Page 59 Debugger Commands Table 3-1. Debugger Commands (Continued) Command Description NOPA Printer Detach PBOOT Bootstrap Operating System Port Format NOPF Port Detach PFLASH Program FLASH Memory Put RTC into Power Save Mode ROMboot Enable NORB ROMboot Disable Register Display REMOTE Remote RESET Cold/Warm Reset Read Loop...
  • Page 60: Diagnostic Tests

    PPCBug Firmware Although a command to allow the erasing and reprogramming of Flash memory is available to you, keep in mind that reprogramming any portion of Flash memory will erase everything currently contained in Flash, Caution including the PPCBug debugger. Note, however, that Flash bank A and Flash bank B both contain the PPCBug debugger.
  • Page 61: Modifying The Environment

    Modifying the Environment Table 3-2. Diagnostic Test Groups (Continued) Command Description NCR 53C8xx SCSI-2 I/O Processor Tests* PAR8730x Parallel Interface (PC8730x) Test* UART Serial Input/Output Tests PCIBUS PCI/PMC Generic Tests Local RAM Tests M48Txxx Timekeeping Tests Serial Communications Controller (Z85C230) Tests* VGA543x Video Diagnostics Tests* VME2...
  • Page 62: Cnfg - Configure Board Information Block

    MPU Clock Speed = "300" Ethernet Address = 0001AF26A464 Local SCSI Identifier = "07" System Serial Number = " nnnnnnn " System Identifier = "Motorola MVME2300SC" License Identifier = " nnnnnnnn " PPC-Bug> The parameters that are quoted are left-justified character (ASCII) strings padded with space characters, and the quotes (") are displayed to indicate...
  • Page 63: Env - Set Environment

    Modifying the Environment The Board Information Block is factory-configured before shipment. There is no need to modify block parameters unless the NVRAM is corrupted. Refer to the MVME2300 Series VME Processor Module Programmer’s Reference Guide for the actual location and other information about the Board Information Block.
  • Page 64: Configuring The Ppcbug Parameters

    PPCBug Firmware Configuring the PPCBug Parameters The parameters that can be configured using ENV are: Bug or System environment [B/S] = B? Bug is the mode where no system type of support is displayed. However, system-related items are still available. (Default) System is the standard mode of operation, and is the default mode if NVRAM should fail.
  • Page 65 Modifying the Environment Probe System for Supported I/O Controllers [Y/N] = Y? Accesses will be made to the appropriate system buses (e.g., VMEbus, local MPU bus) to determine the presence of supported controllers. (Default) Accesses will not be made to the VMEbus to determine the presence of supported controllers.
  • Page 66 PPCBug Firmware Primary SCSI Bus Negotiations Type [A/S/N] = A? Asynchronous SCSI bus negotiation. (Default) Synchronous SCSI bus negotiation. None. Primary SCSI Data Bus Width [W/N] = N? Wide SCSI (16-bit bus). Narrow SCSI (8-bit bus). (Default) Secondary SCSI identifier = 07? Select the identifier.
  • Page 67 Modifying the Environment Auto Boot Enable [Y/N] = N? The Autoboot function is enabled. The Autoboot function is disabled. (Default) Auto Boot at power-up only [Y/N] = N? Autoboot is attempted at power-up reset only. Autoboot is attempted at any reset. (Default) Auto Boot Scan Enable [Y/N] = Y? If Autoboot is enabled, the Autoboot process attempts...
  • Page 68 PPCBug Firmware “bootable” partition. That is then the partition that will be booted. Other acceptable values are 1, 2, 3, or 4. In these four cases, the partition specified will be booted without searching. Auto Boot Abort Delay = 7? The time in seconds that the Autoboot sequence will delay before starting the boot.
  • Page 69 Modifying the Environment ROM Boot Direct Starting Address = FFF00000? The first location tested when PPCBug searches for a ROMboot module. (Default = $FFF00000) ROM Boot Direct Ending Address = FFFFFFFC? The last location tested when PPCBug searches for a ROMboot module.
  • Page 70 PPCBug Firmware Network Auto Boot Configuration Parameters Offset (NVRAM) = 00001000? The address where the network interface configuration parameters are to be saved/retained in NVRAM; these parameters are the necessary parameters to perform an unattended network boot. A typical offset might be $1000, but this value is application-specific.
  • Page 71 Modifying the Environment DRAM Speed in NANO Seconds = 50? The default setting for this parameter will vary depending on the speed of the DRAM memory parts installed on the board. The default is set to the slowest speed found on the available banks of DRAM memory. ROM First Access Length (0 - 31) = 10? This is the value programmed into the“ROMFAL”...
  • Page 72 PPCBug Firmware DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O? DRAM parity is enabled upon detection. (Default) DRAM parity is always enabled. DRAM parity is never enabled. This parameter (above) also applies to enabling ECC for DRAM. Note L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O? L2 Cache parity is enabled upon detection.
  • Page 73: Configuring The Vmebus Interface

    Modifying the Environment Serial Startup Code LF Enable [Y/N]=N? The list of LED/serial codes is included in the section on MPU, Hardware, and Firmware Initialization in Chapter 1 of the PPCBug Firmware Package User’s Manual. Configuring the VMEbus Interface ENV asks the following series of questions to set up the VMEbus interface for the MVME2300SC modules.
  • Page 74 PPCBug Firmware PCI Slave Image 1 Control = C0820000? The configured value is written into the LSI1_CTL register of the Universe chip. PCI Slave Image 1 Base Address Register = 01000000? The configured value is written into the LSI1_BS register of the Universe chip.
  • Page 75 Modifying the Environment PCI Slave Image 3 Bound Address Register = 30000000? The configured value is written into the LSI3_BD register of the Universe chip. PCI Slave Image 3 Translation Offset = D0000000? The configured value is written into the LSI3_TO register of the Universe chip.
  • Page 76 PPCBug Firmware VMEbus Slave Image 1 Translation Offset = 00000000? The configured value is written into the VSI1_TO register of the Universe chip. VMEbus Slave Image 2 Control = 00000000? The configured value is written into the VSI2_CTL register of the Universe chip.
  • Page 77 Modifying the Environment Special PCI Slave Image Register = 00000000? The configured value is written into the SLSI register of the Universe chip. Master Control Register = 80C00000? The configured value is written into the MAST_CTL register of the Universe chip. Miscellaneous Control Register = 52060000? The configured value is written into the MISC_CTL register of the Universe chip.
  • Page 78 PPCBug Firmware 3-26 Computer Group Literature Center Web Site...
  • Page 79: Introduction

    4Functional Description Introduction This chapter describes the MVME2300SC VME processor module on a block diagram level. The Summary of Features provides an overview of the MVME2300SC, followed by a detailed description of several blocks of circuitry. Figure 4-1 shows a block diagram of the overall board architecture.
  • Page 80 Functional Description Table 4-1. MVME2300SC Features (Continued) Feature Description Status LEDs Four: Board Fail , System Controller ( ), Fuses ( (BFL) SCON One 16-bit timer in W83C553 PCI/ISA bridge; four 32-bit timers in Raven (MPIC) device Timers Watchdog timer provided in SGS-Thomson M48T559 Software interrupt handling via Raven (PCI/MPU bridge) and Winbond Interrupts (PCI/ISA bridge) controllers...
  • Page 81: General Description

    General Description General Description The MVME2300SC is a VME processor module equipped with a ® PowerPC 604 microprocessor. As described in the Features section, the MVME2300SC offers many standard features desirable in a computer system — among them Ethernet and debug ports, Boot ROM, Flash memory, DRAM, and an interface for two PCI Mezzanine Cards (PMCs) —...
  • Page 82: I/O Implementation

    Functional Description The Raven bridge controller ASIC provides the bridge between the PowerPC microprocessor bus and the PCI local bus. Electrically, the Raven chip is a 64-bit PCI connection. Four programmable map decoders in each direction provide flexible addressing between the PowerPC microprocessor bus and the PCI local bus.
  • Page 83: Asics

    General Description The Peripheral Component Interface (PCI ) local bus is a key feature. In addition to the on-board local bus peripherals, the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card). ASICs The following ASICs are used on the MVME2300SC: Universe ASIC (VMEbus interface).
  • Page 84: Figure 4-1. Mvme2300Sc Block Diagram

    Functional Description Debug Connector DRAM 16/32/64/128M Clock Generator FLASH 1M to 5M System Processor Registers MPC604 PIB & MPIC Memory Controller Raven ASIC Falcon Chipset 33MHz 32/64-bit PCI Local Bus VME Bridge Ethernet W83c553 Universe Registers Buffers RTC/NVRAM/WD M48T559 TL16C550 UART VME P2 VME P1...
  • Page 85: Dram Latency

    General Description The block diagram for the memory interface is shown in the following figure. Memory Controller Falcon to 128M ECC DRAM Buffers 16M to 128M Flash Buffers Buffers 1M to 5M 2390 9810 Figure 4-2. Memory Block Diagram DRAM Latency The ECC memory access latency times for 60ns, fast page DRAMs are shown in the following table.
  • Page 86: Table 4-4. Ppc604-To-Dram Timing - 50Ns Edo Devices

    Functional Description Table 4-3. PPC604-Bus-to-DRAM Timing — 60ns Page Devices (Continued) Clock Periods Required for: Total Access Type Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4-Beat Read after 4-Beat Read 11/7 (misaligned) 4-Beat Write after Idle 4-Beat Write after 4-Beat Write 10/6 (Quad-word aligned) 1-Beat Read after Idle...
  • Page 87: Flash Memory

    General Description Table 4-4. PPC604-to-DRAM Timing — 50ns EDO Devices (Continued) Clock Periods Required for: Total Access Type Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4-Beat Read after Idle (Quad-word misaligned) 4-Beat Read after 4-Beat Read (Quad-word aligned) 4-Beat Read after 4-Beat Read (misaligned) 4-Beat Write after Idle...
  • Page 88: Flash Latency

    Functional Description Bank B consists of 1MB of 8-bit Flash memory in two 32-pin PLCC 8-bit sockets. Bank A consists of four 16-bit Smart Voltage SMT devices populated with 8Mbit Flash devices (for a total of 4MB). Only 32-bit writes are supported for this bank of Flash.
  • Page 89: Ethernet Interface

    General Description Table 4-5. PowerPC604-Bus-to-Flash Timing — Bank B (16-bit Port) Clock Periods Required for: Total Access type Clocks 1st Beat Beat Beat Beat 4-Beat Read 4-Beat Write 1-Beat Read (2 bytes to 8 bytes) 1-Beat Read (1 byte) 1-Beat Write Ethernet Interface The MVME2300SC module uses Digital Equipment’s DECchip 21143 PCI Fast Ethernet LAN controller to implement an Ethernet interface that...
  • Page 90: Pci Mezzanine Card (Pmc) Interface

    Functional Description The unique Ethernet address is set at the factory and should Note not be changed. Any attempt to change this address may create node or bus contention and thereby render the board inoperable. If the data in NVRAM is lost, use the number on the label in the PMC connector keepout area to restore it.
  • Page 91: Pmc Slot 1 (Single-Width Pmc)

    General Description Refer to Chapter 5 for the pin assignments of the PMC connectors. For detailed programming information, refer to the PCI bus descriptions in the MVME2300 Series VME Processor Module Programmer’s Reference Guide and to the user documentation for the PMC modules you intend to use.
  • Page 92: Pmc Slots 1 And 2 (Double-Width Pmc)

    Functional Description PMC Slots 1 and 2 (Double-Width PMC) PMC slots 1 and 2 with a double-width PMC have the following characteristics: PCI Mezzanine Card (PMC) Mezzanine Type Double width, standard depth (150mm x 150 mm) Mezzanine Size with front panel J11 to J14 and J21 to J24 (32/64-Bit PCI) with front PMC Connectors and rear I/O...
  • Page 93: Asynchronous Debug Port

    General Description Maximum performance is achieved with D64 Multiplexed Block Transfers (MBLT). The on-chip DMA channel should be used to move large blocks of data to/from the VMEbus. The Universe should be able to reach 50MB/second in 64-bit MBLT mode. The MVME2300SC interfaces to the VMEbus via the P1 and P2 backplane connectors, which use three-row 96-pin connectors as specified in the VMEbus standard.
  • Page 94: Real-Time Clock/Nvram/Timer Function

    Functional Description – The PMC slot ISA bus arbitration for DMA devices ISA interrupt mapping for four PCI interrupts Interrupt controller functionality to support 14 ISA interrupts Edge/level control for ISA interrupts Seven independently programmable DMA channels One 16-bit timer Three interval counters/timers Accesses to the configuration space for the PIB controller are performed by way of the CONADD and CONDAT (Configuration Address and Data)
  • Page 95: Pci Host Bridge

    General Description VME Processor Module Programmer’s Reference Guide and to the M48T559 data sheet for detailed programming and battery life information. PCI Host Bridge The Raven ASIC provides the bridge function between the MPC604 processor bus and the PCI Local Bus. It provides 32-bit addressing and 64- bit data.
  • Page 96: Interval Timers

    Functional Description Interval Timers The PIB controller has three built-in counters that are equivalent to those found in an 82C54 programmable interval timer. The counters are grouped into one timer unit, Timer 1, in the PIB controller. Each counter output has a specific function: Counter 0 is associated with interrupt request line IRQ0.
  • Page 97: Connectors

    General Description Connectors The MVME2300SC interfaces to the VMEbus via P1 and P2, which are implemented with the three-row 96-pin connectors specified in the IEEE P1014-1987 VMEbus specification. The board also draws +5V, +12V, and 12V power from the VMEbus backplane through these two connectors. −...
  • Page 98: Status Indicators

    Functional Description Status Indicators The MVME2300SC front panel has four LED (light-emitting diode) status indicators: (DS1, yellow). Board failure; lights when the BRDFAIL signal line is active. ∗ (DS2, green). CPU activity; lights when the DBB∗ (Data Bus Busy) signal line on the processor bus is SCON active.
  • Page 99: Connector Pin Assignments

    The tables in this chapter furnish pin assignments only. For detailed descriptions of the interconnect signals, consult the support information for the MVME2300SC (available through your Motorola sales office). VMEbus Connectors (P1, P2) Two three-row 96-pin DIN type connectors, P1 and P2, supply the interface between the base board and the VMEbus.
  • Page 100: Table 5-1. Vmebus Connector P1 Pin Assignments

    Pin Assignments Table 5-1. VMEbus Connector P1 Pin Assignments Row A Row B Row C VBBSY∗ VBCLR∗ VACFAIL∗ VD10 VBGIN0∗ VD11 VBGOUT0∗ VD12 VBGIN1∗ VD13 VBGOUT1∗ VD14 VBGIN2∗ VD15 VBGOUT2∗ VSYSCLK VBGIN3∗ VSYSFAIL∗ VBGOUT3∗ VBERR∗ VDS1∗ VBR0∗ VSYSRESET∗ VDS0∗ VBR1∗ VLWORD∗...
  • Page 101: Table 5-2. Vmebus Connector P2 Pin Assignment

    Connector Pin Assignments Table 5-2. VMEbus Connector P2 Pin Assignment ROW A ROW B ROW C PMC1/2_2 (J14/J24-2) PMC1/2_1 (J14/J24-1) PMC1/2_4 (J14/J24-4) PMC1/2_3 (J14/J24-3) PMC1/2_6 (J14/J24-6) Not Used PMC1/2_5 (J14/J24-5) PMC1/2_8 (J14/J24-8) VA24 PMC1/2_7 (J14/J24-7) PMC1/2_10 (J14/J24-10) VA25 PMC1/2_9 (J14/J24-9) PMC1/2_12 (J14/J24-12) VA26 PMC1/2_11 (J14/J24-11)
  • Page 102: Serial Port Connector - Debug (J2)

    Pin Assignments Serial Port Connector - DEBUG (J2) A standard Micro D9 connector located on the front panel of the MVME2300SC provides the interface to the asynchronous serial debug port. The pin assignments for this connector are as follows: Table 5-3. DEBUG (J2) Connector Pin Assignments DCD_EXT RD_EXT TD_EXT...
  • Page 103: Cpu Debug Connector - J1

    Connector Pin Assignments CPU Debug Connector - J1 One 190-pin Mictor connector with a center row of power and ground pins is used to provide access to the Processor Bus and some miscellaneous signals. The pin assignments for this connector are as follows: Table 5-5.
  • Page 104 Pin Assignments Table 5-5. CPU Debug (J1) Connector Pin Assignments (Continued) PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PA20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PD32 PD33 PD34 PD35 PD36 PD37 Computer Group Literature Center Web Site...
  • Page 105 Connector Pin Assignments Table 5-5. CPU Debug (J1) Connector Pin Assignments (Continued) PD38 PD39 PD40 PD41 PD42 PD43 PD44 PD45 PD46 PD47 PD48 PD49 PA50 PD51 PD52 PD53 PD54 PD55 PD56 PD57 PD58 PD59 PD60 PD61 PD62 PD63 DPAR0 DPAR1 DPAR2 DPAR3 DPAR4...
  • Page 106 Pin Assignments Table 5-5. CPU Debug (J1) Connector Pin Assignments (Continued) TSIZ0 TSIZ1 TSIZ2 CI∗ WT∗ CSE0 GLOBAL∗ CSE1 SHARED∗ DBWO∗ +3.3V AACK∗ TS∗ ARTRY∗ XATS∗ DRTRY∗ TBST∗ TA∗ TEA∗ DBG∗ DBB∗ ABB∗ TCLK_OUT MPUBG0∗ MPUBR0∗ Computer Group Literature Center Web Site...
  • Page 107 Connector Pin Assignments Table 5-5. CPU Debug (J1) Connector Pin Assignments (Continued) MPUBR1∗ IRQ0∗ MPUBG1∗ MCHK0∗ IRQ1∗ SMI∗ MCHK1∗ CKSTPI∗ L2BR∗ CKSTPO∗ L2BG∗ HALTED CLAIM∗ TLBISYNC∗ TBEN0 Not Used DRVMOD0 DRVMOD1 NAPRUN SRST1∗ QREQ∗ SRESET∗ QACK∗ HRESET∗ CPUTDO CPUTDI MPUCLK4 CPUTCK MPUCLK4 CPUTMS...
  • Page 108: Pci Expansion Connector - J6

    Pin Assignments PCI Expansion Connector - J6 One 114-pin Mictor connector with center row of power and ground pins is used to provide PCI/PMC expansion capability. The pin assignments for this connector are as follows: Table 5-6. J6 - PCI Expansion Connector (J6) Pin Assignments +3.3V +3.3V PCICLK...
  • Page 109 Connector Pin Assignments Table 5-6. J6 - PCI Expansion Connector (J6) Pin Assignments (Continued) PCIRST∗ C/BE1∗ C/BE0∗ C/BE3∗ C/BE2∗ AD11 AD10 AD13 AD12 AD15 AD14 AD17 AD16 AD19 AD18 AD21 AD20 AD23 AD22 AD25 AD24 AD27 AD26 AD29 AD28 AD31 AD30 5-11...
  • Page 110: Pci Mezzanine Card Connectors - J11 Through J14

    Pin Assignments Table 5-6. J6 - PCI Expansion Connector (J6) Pin Assignments (Continued) PAR64 Reserved C/BE5∗ C/BE4∗ C/BE7∗ C/BE6∗ AD33 AD32 AD35 AD34 AD37 AD36 AD39 AD38 AD41 AD40 AD43 AD42 AD45 AD44 AD47 AD46 AD49 AD48 AD51 AD50 AD53 AD52 AD55 AD54...
  • Page 111: Table 5-7. J11 - J12 Pmc1 Connector Pin Assignments

    Connector Pin Assignments Table 5-7. J11 - J12 PMC1 Connector Pin Assignments –12V +12V TRST∗ INTA∗ PMC1TDO INTB∗ INTC∗ PMC2TDO PMC1P∗ Not Used PMCINTD∗ Not Used Not Used Not Used Not Used Pull-up +3.3V PCICLK6 PCIRST∗ Pull-down PMC1GNT∗ +3.3V Pull-down PMC1REQ∗...
  • Page 112: Table 5-8. J13 - J14 Pmc1 Connector Pin Assignments

    Pin Assignments Table 5-8. J13 - J14 PMC1 Connector Pin Assignments Reserved MC (P2-C1) SD_15 (P2-A1) C/BE7∗ SD_14 (P2-C2) SD_13 (P2-A2) C/BE6∗ C/BE5∗ SD_12 (P2-C3) GND (P2-A3) C/BE4∗ SD_11 (P2-C4) SD_10 (P2-A4) PAR64 SD _9 (P2-C5) SD_8 (P2-A5) AD63 AD62 SD_7 (P2-C6) GND (P2-A6) AD61...
  • Page 113: Pci Mezzanine Card Connectors - J21 Through J24

    Connector Pin Assignments PCI Mezzanine Card Connectors - J21 through J24 Four 64-pin SMT connectors, J21 through J24, supply 32/64-bit PCI interfaces and P2 I/O between the MVME2300SC board and an optional add-on PCI Mezzanine Card (PMC) in PMC Slot 2. The pin assignments for PMC Slot 2 are listed in the following two tables.
  • Page 114: Table 5-9. J21 And J22 Pmc2 Connector Pin Assignments

    Pin Assignments Table 5-9. J21 and J22 PMC2 Connector Pin Assignments –12V +12V TRST# INTA# PMC2TDO INTB# INTC# PCIXTDO PMC2P# Not Used PMCINTC# Not Used Not Used Not Used Not Used Pull-up +3.3V PCICLK7 PCIRST# Pull-down PMC2GNT# +3.3V Pull-down PMC2REQ# Not Used AD31 AD30...
  • Page 115: Table 5-10. J23 And J24 Pmc2 Connector Pin Assignments

    Connector Pin Assignments Table 5-10. J23 and J24 PMC2 Connector Pin Assignments Reserved MC (P2-C1) SD_15 (P2-A1) C/BE7# SD_14 (P2-C2) SD_13 (P2-A2) C/BE6# C/BE5# SD_12 (P2-C3) GND (P2-A3) C/BE4# SD_11 (P2-C4) SD_10 (P2-A4) PAR64 SD _9 (P2-C5) SD_8 (P2-A5) AD63 AD62 SD_7 (P2-C6) GND (P2-A6)
  • Page 116 Pin Assignments 5-18 Computer Group Literature Center Web Site...
  • Page 117: Appendix A Specifications

    ASpecifications Board Specifications The following table lists the general specifications for the MVME2300SC VME processor module. Subsequent sections detail cooling requirements and EMC regulatory compliance. A complete functional description of the MVME2300SC boards appears in Chapter 4. Specifications for the optional PMCs can be found in the documentation for those modules.
  • Page 118 Specifications Table A-1. MVME2300SC Specifications (Continued) Characteristics Specifications Physical dimensions Height Double-high VME board, 9.2 in. (233 mm) (base board only) Front panel width 0.8 in. (19.8 mm) Front panel height 10.3 in. (261.7 mm) Depth 6.3 in. (160 mm) PCI Mezzanine Card Address/Data A32/D32/D64, PMC PN1-4 connectors...
  • Page 119: Cooling Requirements

    (base board and modules) at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VME system chassis. Twenty-five-watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration.
  • Page 120: Emc Regulatory Compliance

    Specifications While the exact amount of airflow required for cooling depends on the ambient air temperature and the type, number, and location of boards and other heat sources, adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the module. Less airflow is required to cool the module in environments having lower maximum ambients.
  • Page 121: Solving Startup Problems

    BTroubleshooting Solving Startup Problems In the event of difficulty with your MVME2300SC VME processor module, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.) The self- tests may not run in all user-customized environments.
  • Page 122 Troubleshooting Table B-1. Troubleshooting MVME2300SC Modules (Continued) Condition Possible Problem Try This: II. There is a display A. The keyboard or Recheck the keyboard and/or mouse connections and power. on the terminal, mouse may be but input from the connected keyboard (and/or incorrectly.
  • Page 123 Solving Startup Problems Table B-1. Troubleshooting MVME2300SC Modules (Continued) Condition Possible Problem Try This: IV. Continued 2. At the command line prompt, type in: env;d <CR> This sets up the default parameters for the debugger environment. 3. When prompted to Update Non-Volatile RAM, type in: y <CR>...
  • Page 124 Troubleshooting Table B-1. Troubleshooting MVME2300SC Modules (Continued) Condition Possible Problem Try This: VI. The board has A. There may be 1. Document the problem and return the board for service. failed one or some fault in the 2. Phone 1-800-222-5640. more of the tests board hardware or listed above, and...
  • Page 125: Motorola Computer Group Documents

    CRelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting MCG’s World Wide Web literature site,...
  • Page 126: Manufacturers' Documents

    Publication Document Title and Source Number PowerPC 604 RISC Microprocessor Technical Summary MPC604E/D Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 PowerPC 604 RISC Microprocessor User’s Manual MPC604EUM/AD Literature Distribution Center for Motorola...
  • Page 127 Manufacturers’ Documents Publication Document Title and Source Number IBM Microelectronics G522-0290-01 Programming Environment Manual Web Site: PC16550 UART PC16550DV National Semiconductor Corporation Customer Support Center (or nearest Sales Office) 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, California 95052-8090 Telephone: 408-721-5000 Telephone: 1-800-272-9959 21140 Fast Etherworks PCI 10-Flash-100 Ethernet Adapter EK-DE500-OM...
  • Page 128 Related Documentation Publication Document Title and Source Number W83C553 Enhanced System I/O Controller with PCI Arbiter (PIB) W83C553F Winbond Electronics Corporation Winbond Systems Laboratory 2727 North First Street San Jose, CA 95134 Telephone: (408) 943-6666 FAX:(408) 544-1798 M48T559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet M48T559 STMicroelectronics...
  • Page 129: Related Specifications

    Related Specifications Related Specifications For additional information, refer to the following table for related specifications. For your convenience, a source for the listed document is also provided. It is important to note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
  • Page 130 Third Edition, Version 1.0, Volumes I and II International Business Machines Corporation PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 Morgan Kaufmann Publishers, Inc.
  • Page 131 Glossary An Ethernet implementation in which the physical medium is a 10Base-5 doubly shielded, 50-ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters (also referred to as thicknet). Also known as thick Ethernet. An Ethernet implementation in which the physical medium is a 10Base-2 single-shielded, 50-ohm RG58A/U coaxial cable capable of...
  • Page 132 Glossary A byte-ordering method in memory where the address n of a word big-endian corresponds to the most significant byte. In an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most significant byte.
  • Page 133 A local area network standard that uses radio frequency signals Ethernet carried by coaxial cables. The DRAM controller chip developed by Motorola for the Falcon MVME2600 and MVME3600 series of boards. It is intended to be used in sets of two to provide the necessary interface between the Power PC60x bus and the 144-bit ECC DRAM (system memory array) and/or ROM/Flash.
  • Page 134 In an addressed memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most significant byte. Motorola’s component designation for the PowerPC 604 MPC604 microprocessor. Multi-Processor Interrupt Controller...
  • Page 135 Instructions can be sent simultaneously to three types of independent execution units (branch units, fixed-point units, and floating-point units), where they can execute concurrently, but finish out of order. PowerPC is used by Motorola, Inc. under license from IBM. Random-Access Memory. The temporary memory that a computer uses to hold the instructions and data currently being worked with.
  • Page 136 Glossary Signal Computing System Architecture. A hardware model for SCSA computer telephony servers. A key SCSA element is a TDM (time division multiplexed) telephony bus for voice and video signals, known as the SCbus™ in VME implementations of this architecture. Small Computer Systems Interface.
  • Page 137 Ethernet See 10Base-T. twisted-pair Ethernet Universal Asynchronous Receiver/Transmitter UART ASIC developed by Tundra in consultation with Motorola which Universe provides the complete interface between the PCI bus and the VMEbus. Video Electronics Standards Association (or VL bus). An internal...
  • Page 138 Glossary GL-8 Computer Group Literature Center Web Site...
  • Page 139 Index board Numerics architecture 10/100 BASET port 4-20 configuration 16/32-bit timers 4-18 dimensions features abort process 2-11 layout, MVME2300SC address pipelining (PowerPC bus) 4-8, placement 1-19 altitude (operating) preparation ambient air temperature (effect on cooling) booting the system 2-7, 2-8, BREAK key 2-11 arguments, firmware command...
  • Page 140 Index configuring hardware EMC regulatory compliance PMCs 1-10, environmental parameters PPCBug parameters 3-12 ESD (electrostatic discharge), precautions VMEbus interface 3-21 against connector pin assignments Ethernet console terminal, preparing 1-20 interface 4-11 cooling requirements station address 4-11 counters 4-17 features date and time, setting hardware debug firmware, PPCBug Universe ASIC...
  • Page 141 IACK (interrupt acknowledge) signal 1-19 manufacturers’ documents indicators (front panel) memory initial conditions block diagram installation considerations 1-21 quantity available installing requirements, debugger multiple MVME2300SC boards 1-21 sizing function, enabling 3-18 MVME2300SC in chassis 1-18 MPIC (MultiProcessor Interrupt Controller) PMC carrier board 1-17 4-17 PMC modules 1-11,...
  • Page 142 Index pin assignments, connector PMC slot 1 Raven MPU/PCI bus bridge controller ASIC connector pin assignments, J11 and J12 4-4, 4-15 5-13 readable jumpers (J10) connector pin assignments, J13 and J14 real-time clock/NVRAM/timer function 4-16 5-14 regulatory compliance PMC slot 2 regulatory guidelines connector pin assignments, J21 and J22 related documentation...
  • Page 143 status indicators (front panel) 4-20 stop bits per character (serial port) 1-20 vibration (operating) storage temperature VME processor module switches (front panel) board layout switching directories 2-11 VMEbus 4-3, SYSFAIL∗ signal 3-13 address/data configurations 1-21 system connectors console setup system controller selection (J9) console, connecting 1-20 Universe ASIC and...
  • Page 144 Index IN-6 Computer Group Literature Center Web Site...

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