I2C Transmitter Data Register - Motorola MVME2400 Series Programmer's Reference Manual

System Memory Controller (SMC)

I2C Transmitter Data Register

Address
$FEF800A8
Bit
3
Name
Operation
READ ZERO
Reset
X
3-64
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READ ZERO
X
I2_DATAWR The I2_DATAWR contains the transmit byte for I
data transfers. If a value is written to I2_DATAWR when the i2_start
2
and i2_enbl bits in the I C Control Register are set, a start sequence is
generated immediately followed by the transmission of the contents of
the I2_DATAWR to the responding slave device. The
I2_DATAWR[24:30] is the device address, and the
I2_DATAWR[31] is the WR/RD bit (0=WRite, 1=ReaD). After a
start sequence with I2_DATAWR[31]=0, subsequent writes to the I
Transmitter Data Register will cause the contents of I2_DATAWR to
be transmitted to the responding slave device. After a start sequence
with I2_DATAWR[31]=1, subsequent writes to the I
Data Register (data=don't care) will cause the responding slave device
2
to transmit data to the I C Receiver Data Register. If a value is written
to I2_DATAWR (data=don't care) when the i2_stop and i2_enbl bits
2
in the I C Control Register are set, a stop sequence is generated.
I2_DATAWR
READ ZERO READ/WRITE
X 0 PL
2
C Transmitter
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2
C
2
C