Mpic I/O Base Address Register - Motorola MVME2400 Series Programmer's Reference Manual
Vme processor module
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Also See for MVME2400 Series:
- Installation and use manual (175 pages) ,
- Installation and user manual (20 pages)
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MPIC I/O Base Address Register
2
Offset
$10
Bit
3
3
1
0
Name
MIBAR
BASE
Operation R/W
Reset
$0000
The MPIC I/O Base Address Register (MIBAR) controls the mapping of
the MPIC control registers in PCI I/O space.
2-96
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2
2
2
2
2
2
2
2
2
2
1
9
8
7
6
5
4
3
2
1
0
9
IO/MEM (IO Space Indicator) This bit is hard-wired to a logic one to
indicate PCI I/O space.
RES (Reserved) This bit is hard-wired to zero.
BASE (Base Address) These bits define the I/O space base address of
the MPIC control registers. The MIBAR decoder is disabled when the
BASE value is zero.
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$0000
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