Motorola MVME2300 Series Manuals

Manuals and User Guides for Motorola MVME2300 Series. We have 2 Motorola MVME2300 Series manuals available for free PDF download: Programmer's Reference Manual, Installation And Use Manual

Motorola MVME2300 Series Programmer's Reference Manual (282 pages)

VME Processor Module

Brand: Motorola | Category: Network Hardware | Size: 2.73 MB

Safety Summary
3
Lithium Battery Caution
4
Table of Contents
7
About this Manual

19
- Summary of Changes
  20
- Comments and Suggestions
  21
- Overview of Contents
  21
- Conventions Used in this Manual
  22
CHAPTER 1 Board Description and Memory Maps

25
CHAPTER 2 Raven PCI Bridge ASIC

71
- Introduction
  71
- Features
  71
- Table 2-1. Features of the Raven ASIC
  71
- Block Diagram
  72
- Figure 2-1. Raven Block Diagram
  73
- Functional Description
  74
  - MPC Bus Interface
    74
    
    MPC Address Mapping
    74
    
    Figure 2-2. MPC-To-PCI Address Decoding
    75
    
    Figure 2-3. MPC to PCI Address Translation
    76
    
    MPC Slave
    76
    
    Table 2-2. Command Types - MPC Slave Response
    77
    
    MPC Master
    78
    
    MPC Write Posting
    78
    
    Table 2-3. MPC Transfer Types
    79
    
    MPC Arbiter
    80
    
    MPC Bus Timer
    80
  - PCI Interface
    80
    
    PCI Address Mapping
    81
    
    Figure 2-4. PCI to MPC Address Decoding
    82
    
    Figure 2-5. PCI to MPC Address Translation
    83
    
    PCI Slave
    84
    
    Table 2-4. Command Types - PCI Slave Response
    85
    
    PCI Master
    87
    
    PCI Write Posting
    87
    
    Table 2-5. PCI Master Command Codes
    88
    
    Generating PCI Cycles
    91
    
    Figure 2-6. PCI Spread I/O Address Translation
    92
  - Endian Conversion
    95
    
    When MPC Devices Are Big-Endian
    95
    
    Figure 2-7. Big- to Little-Endian Data Swap
    96
    
    Raven Registers and Endian Mode
    97
    
    Table 2-6. Address Modification for Little-Endian Transfers
    97
    
    When MPC Devices Are Little-Endian
    97
  - Error Handling
    98
  - Transaction Ordering
    99
- Raven Registers
  100
  - MPC Registers
    100
    
    Table 2-7. Raven MPC Register Map
    101
    
    Vendor ID/Device ID Registers
    102
    
    General Control-Status/Feature Registers
    103
    
    Revision ID Register
    103
    
    MPC Arbiter Control Register
    106
    
    Prescaler Adjust Register
    106
    
    MPC Error Enable Register
    107
    
    MPC Error Status Register
    109
    
    MPC Error Address Register
    110
    
    MPC Error Attribute Register - MERAT
    111
    
    MPC Slave Address (0,1 and 2) Registers
    113
    
    PCI Interrupt Acknowledge Register
    113
    
    MPC Slave Address (3) Register
    114
    
    MPC Slave Offset/Attribute (0,1 and 2) Registers
    115
    
    MPC Slave Offset/Attribute (3) Registers
    116
    
    General-Purpose Registers
    117
  - PCI Registers
    117
    
    Table 2-8. Raven PCI Configuration Register Map
    118
    
    Table 2-9. Raven PCI I/O Register Map
    119
    
    Vendor ID/ Device ID Registers
    119
    
    PCI Command/ Status Registers
    120
    
    I/O Base Register
    122
    
    Revision ID/ Class Code Registers
    122
    
    Memory Base Register
    123
    
    PCI Slave Address (0,1,2 and 3) Registers
    124
    
    PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
    125
    
    CONFIG_ADDRESS Register
    126
    
    CONFIG_DATA Register
    128
- Raven Interrupt Controller
  130
  - Architecture
    130
    
    Interrupt Source Priority
    131
    
    Processor's Current Task Priority
    131
    
    Readability of CSR
    131
  - Features
    130
  - Compatibility
    132
  - Interprocessor Interrupts (IPI)
    132
  - Nesting of Interrupt Events
    132
  - Spurious Vector Generation
    132
  - Raven-Detected Errors
    133
  - Timers
    133
  - Interrupt Delivery Modes
    134
  - Figure 2-8. Ravenmpic Block Diagram
    135
- Block Diagram Description
  135
  - Program-Visible Registers
    136
  - Interrupt Pending Register (IPR)
    136
  - Interrupt Selector (IS)
    136
  - Interrupt Request Register (IRR)
    137
  - In-Service Register (ISR)
    137
  - Interrupt Router
    137
  - Table 2-10. Ravenmpic Register Map
    139
- MPIC Registers
  139
  - Ravenmpic Registers
    139
  - Feature Reporting Register
    143
  - Global Configuration Register
    144
  - Vendor Identification Register
    145
  - Processor Init Register
    145
  - IPI Vector/Priority Registers
    146
  - Spurious Vector Register
    147
  - Timer Frequency Register
    147
  - Timer Current Count Registers
    148
  - Timer Base Count Registers
    148
  - Timer Vector/Priority Registers
    149
  - Timer Destination Registers
    150
  - External Source Vector/Priority Registers
    151
  - External Source Destination Registers
    152
  - Raven-Detected Errors Vector/Priority Register
    153
  - Raven-Detected Errors Destination Register
    154
  - Interprocessor Interrupt Dispatch Registers
    154
  - Interrupt Task Priority Registers
    155
  - Interrupt Acknowledge Registers
    156
  - End-Of-Interrupt Registers
    156
- Programming Notes
  157
  - External Interrupt Service
    157
  - Reset State
    158
  - Interprocessor Interrupts
    159
  - Dynamically Changing I/O Interrupt Configuration
    159
  - EOI Register
    160
  - Interrupt Acknowledge Register
    160
    
    Current Task Priority Level
    160
    
    Mode
    160
  - Architectural Notes
    161
    
    Features
    163
    
    Introduction
    163
    
    Table 3-1. Features of the Falcon Chip Set
    163
CHAPTER 3 Falcon ECC Memory Controller Chip Set

164
- Block Diagrams
  164
  - Figure 3-1. Falcon Pair Used with DRAM in a System
    164
  - Figure 3-2. Falcon Internal Data Paths (Simplified)
    165
  - Figure 3-3. Overall DRAM Connections
    166
  - Bit Ordering Convention
    167
  - Functional Description
    167
  - Performance
    167
    
    Four-Beat Reads/Writes
    167
    
    DRAM Speeds
    168
    
    Single-Beat Reads/Writes
    168
    
    Table 3-2. Powerpc 60 X Bus to DRAM Access Timing - 70Ns Page Devices
    169
    
    Table 3-3. Powerpc 60 X Bus to DRAM Access Timing - 60Ns Page Devices
    170
    
    Table 3-4. Powerpc Bus to DRAM Access Timing - 50Ns Hyper Devices
    171
    
    Rom/Flash Speeds
    172
    
    Table 3-5. Powerpc 60X Bus to Rom/Flash Access Timing - 64 Bits (32 Bits Per Falcon)
    172
    
    Table 3-6. Powerpc 60X Bus to Rom/Flash Access Timing - 16 Bits (8 Bits Per Falcon)
    172
  - Powerpc 60X Bus Interface
    173
    
    Cache Coherency
    173
    
    Completing Data Transfers
    173
    
    Responding to Address Transfers
    173
    
    Cache Coherency Restrictions
    174
    
    Cycle Types
    174
    
    L2 Cache Support
    174
    
    Table 3-7. Error Reporting
    175
    
    Error Logging
    176
  - DRAM Tester
    176
  - Rom/Flash Interface
    176
  - Table 3-8. Powerpc 60X to Rom/Flash Address Mapping - Rom/Flash
    178
  - Table 3-9. Powerpc 60X to Rom/Flash Address Mapping - Rom/Flash
    179
  - Refresh/Scrub
    180
    
    Blocks a And/Or B Present, Blocks C and D Not Present
    180
    
    Blocks a And/Or B Present, Blocks C And/Or D Present
    181
  - Chip Defaults
    182
  - DRAM Arbitration
    182
  - CSR Accesses
    183
  - CSR Architecture
    183
    
    External Register Set
    183
    
    Programming Model
    183
  - Figure 3-4. Data Path for Reads from the Falcon Internal Csrs
    184
  - Figure 3-5. Data Path for Writes to the Falcon Internal Csrs
    185
  - Figure 3-6. Memory Map for Byte Reads to CSR
    186
  - Figure 3-7. Memory Map for Byte Writes to Internal Register Set and Test SRAM
    187
  - Figure 3-8. Memory Map for 4-Byte Reads to CSR
    188
  - Figure 3-9. Memory Map for 4-Byte Writes to Internal Register Set and Test SRAM
    188
  - Detailed Register Bit Descriptions
    189
    
    Table 3-10. Register Summary
    190
    
    Vendor/Device Register
    192
    
    Revision ID/ General Control Register
    193
    
    Table 3-11. Ram Spd1,Ram Spd0 and DRAM Type
    194
    
    DRAM Attributes Register
    195
    
    Table 3-12. Block_A/B/C/D Configurations
    196
    
    CLK Frequency Register
    197
    
    DRAM Base Register
    197
    
    ECC Control Register
    198
    
    Error Logger Register
    201
    
    Error Address Register
    204
    
    Scrub/Refresh Register
    205
    
    Table 3-13. Rtest Encodings
    205
    
    Refresh/Scrub Address Register
    206
    
    ROM a Base/Size Register
    207
    
    Table 3-14. ROM Block a Size Encoding
    208
    
    Table 3-16. Read/Write to Rom/Flash
    209
    
    ROM B Base/Size Register
    210
    
    Table 3-17. ROM Block B Size Encoding
    211
    
    Bit Counter
    212
    
    DRAM Tester Control Registers
    212
    
    Test SRAM
    212
    
    Power-Up Reset Status Register 1
    213
    
    Power-Up Reset Status Register 2
    213
    
    External Register Set
    214
  - Register Summary
    189
- Software Considerations
  215
  - Parity Checking on the Powerpc Bus
    215
  - Programming Rom/Flash Devices
    215
  - Writing to the Control Registers
    215
  - Sizing DRAM
    216
  - Table 3-18. Sizing Addresses
    218
  - Table 3-19. Powerpc 60X Address to DRAM Address Mappings
    218
  - Table 3-20. Syndrome Codes Ordered by Bit in Error
    219
  - ECC Codes
    219
  - Table 3-21. Single-Bit Errors Ordered by Syndrome Code
    221
  - Data Paths
    222
    
    Figure 3-10. Powerpc Data to DRAM Data Correspondence
    222
    
    Table 3-22. Powerpc Data to DRAM Data Mapping
    223
    
    Features
    225
    
    Introduction
    225
    
    Table 4-1. Features of the Universe ASIC
    226
    
    Block Diagram
    227
    
    Functional Description
    227
    
    Vmebus Interface
    228
CHAPTER 4 Universe (Vmebus to PCI) Chip

228
- Universe as Vmebus Slave
  228
- Figure 4-1. Architectural Diagram for the Universe
  228
- Universe as Vmebus Master
  229
- PCI Bus Interface
  229
  - Universe as PCI Slave
    230
  - Universe as PCI Master
    230
- Interrupter
  230
  - Vmebus Interrupt Handling
    231
- DMA Controller
  231
- Universe Control and Status Registers (UCSR)
  232
  - Universe Register Map
    233
  - Figure 4-2. UCSR Access Mechanisms
    233
  - Table 4-2. Universe Register Map
    234
- Universe Chip Problems after PCI Reset
  238
  - Description
    238
  - Workarounds
    239
- Examples
  240
CHAPTER 5 Programming Details

246
- Interrupt Handling
  246
  - Ravenmpic
    247
  - Table 5-2. Ravenmpic Interrupt Assignments
    247
  - Interrupts
    248
  - Figure 5-2. PIB Interrupt Handler Block Diagram
    249
  - Table 5-3. PIB PCI/ISA Interrupt Assignments
    250
  - ISA DMA Channels
    251
- Exceptions
  252
  - Sources of Reset
    252
  - Table 5-4. Reset Sources and Devices Affected
    253
  - Soft Reset
    253
  - Universe Chip Problems after PCI Reset
    253
  - Table 5-5. Error Notification and Handling
    254
  - Figure 5-3. Big-Endian Mode
    255
- Endian Issues
  255
  - Figure 5-4. Little-Endian Mode
    256
  - PCI Domain
    257
    
    Pci-Scsi
    257
    
    Pci/Ethernet
    257
    
    PCI-Graphics
    258
  - Processor/Memory Domain
    257
  - Role of the Raven ASIC
    257
  - Role of the Universe ASIC
    258
  - Vmebus Domain
    258
- Rom/Flash Initialization
  259
APPENDIX A Related Documentation

261
- Motorola Computer Group Documents
  261
- Manufacturers' Documents
  262
- Related Specifications
  264

Motorola MVME2300 Series Installation And Use Manual (164 pages)

VME Processor Module

Brand: Motorola | Category: Control Unit | Size: 1.61 MB

Table of Contents
7
About this Manual

15
- Summary of Changes
  16
- Overview of Contents
  16
- Comments and Suggestions
  17
- Conventions Used in this Manual
  18
- Terminology
  18
CHAPTER 1 Preparation and Installation

21
CHAPTER 2 Operating Instructions

43
- Introduction
  43
- Applying Power
  43
- Description
  44
  - Switches
    44
    
    Abt (S1)
    45
    
    Rst (S2)
    45
  - Status Indicators
    46
    
    Bfl (Ds1)
    46
    
    Cpu (Ds2)
    46
    
    Pmc (Ds3)
    46
    
    Pmc (Ds4)
    46
  - 10Baset/100Basetx Port
    46
  - DEBUG Port
    47
  - Figure 2-1. MVME2300 DEBUG Port Configuration
    47
  - PMC Slots
    48
    
    PCI Mezzanine Card (PMC Slot 1)
    48
    
    PCI Mezzanine Card (PMC Slot 2)
    48
- Pmcspan
  49
CHAPTER 3 Functional Description

51
- Introduction
  51
- Features
  51
- Table 3-1. MVME2300 Features
  51
- General Description
  53
- Block Diagram
  53
CHAPTER 4 Programming

71
- Introduction
  71
- Memory Maps
  71
- Programming Considerations
  74
  - PCI Arbitration
    74
  - Figure 4-1. Vmebus Master Mapping
    75
  - Interrupt Handling
    76
  - Table 4-2. PCI Arbitration Assignments
    76
  - Figure 4-2. MVME2300 Interrupt Architecture
    77
  - DMA Channels
    78
  - Sources of Reset
    78
  - Endian Issues
    79
    
    Table 4-3. Classes of Reset and Effectiveness
    79
    
    PCI Domain
    80
    
    Processor/Memory Domain
    80
    
    Vmebus Domain
    81
CHAPTER 5 Ppcbug

83
- Ppcbug Overview
  83
- Ppcbug Basics
  83
  - Memory Requirements
    85
  - Ppcbug Implementation
    85
- MPU, Hardware, and Firmware Initialization
  85
- Using Ppcbug
  87
  - Debugger Commands
    88
  - Table 5-1. Debugger Commands
    88
  - Diagnostic Tests
    92
  - Table 5-2. Diagnostic Test Groups
    92
CHAPTER 6 Modifying the Environment

95
- Overview
  95
- CNFG - Configure Board Information Block
  96
- ENV - Set Environment
  97
  - Configuring the Ppcbug Parameters
    97
  - Configuring the Vmebus Interface
    106
APPENDIX A Specifications

111
- Specifications
  111
  - Table A-1. Specifications
    111
- Cooling Requirements
  113
- EMC Regulatory Compliance
  114
APPENDIX B Connector Pin Assignments

115
- Introduction
  115
- Pin Assignments
  115
APPENDIX C Troubleshooting

135
- Solving Startup Problems
  135
  - Table C-1. Troubleshooting Problems
    135
APPENDIX D Related Documentation

139
- Motorola Computer Group Documents
  139
- Manufacturers' Documents
  140
- Related Specifications
  143
- Abbreviations, Acronyms, and Terms to Know
  145

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Motorola MVME2300 Series Manuals

Motorola MVME2300 Series Programmer's Reference Manual (282 pages)

Table of Contents

About this Manual

CHAPTER 1 Board Description and Memory Maps

CHAPTER 2 Raven PCI Bridge ASIC

CHAPTER 3 Falcon ECC Memory Controller Chip Set

CHAPTER 4 Universe (Vmebus to PCI) Chip

CHAPTER 5 Programming Details

APPENDIX A Related Documentation

Motorola MVME2300 Series Installation And Use Manual (164 pages)

Table of Contents

About this Manual

CHAPTER 1 Preparation and Installation

CHAPTER 2 Operating Instructions

CHAPTER 3 Functional Description

CHAPTER 4 Programming

CHAPTER 5 Ppcbug

CHAPTER 6 Modifying the Environment

APPENDIX A Specifications

APPENDIX B Connector Pin Assignments

APPENDIX C Troubleshooting

APPENDIX D Related Documentation

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